Hello team,
I have a couple of questions regarding the external CLK synchronization design requirement.
1) How many CLK pulses are required to complete the synchronization.
2) When the MODE is set low, does the device work with PFM in light load condition in case of putting external CLK on the SYNC pin? (If yes, is there any way to synchronize to the external CLK even in light load condition? Should we set FPWM with the MODE is set high?)
Thanks in advance.
S.Sawamoto
