UCC28951-Q1: Abnormal behaviour in slave configuration

Hello,

It seem that your master clock in master mode is 198 kHz and your sync frequency is 200 kHz.  I think the sync frequency may be too close to the programed master clock frequency.  I would suggest increasing the sync frequency to 220 kHz.  To see things improve.

If your design has sub harmonic oscillation more than likely you do not have enough slope compensation.  The following link will bring you to an application note that goes through the step by step design process in a phase shifted full bridge using the UCC28951.  There is a section that discusses how to setup the slope compensation.  https://www.ti.com/lit/pdf/slua560

Regards,

Hi Mike,

Thank you for your reply.

In master mode Rt is 60K4 connected to Vcc. In this way the output signals have a frequency around 100 KHz. Following what we have discussed about here:

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1234355/ucc28950-questions-about-sync-circuit-showed-in-slua609/4671341?tisearch=e2e-sitesearch&keymatch=%2520user%253A541000#4671341

I've adopted a SYNC signal frequency of 200 KHz, to have the outputs signal frequency at 100 KHz. I think that if I increase the SYNC frequency at 220 KHz then the outputs will go at 110 KHz. Maybe it would be better to increase Rt at for example 75K to have a master clock of 80 KHz? Is there no way to mantain master clock and SYNC derived clock similar?

About the sub-harmonic oscillations, I've noticed that if I decrease further RSUM (to add more compensation) then the  maximum output current decrease, it seems that the summing of the two ramps hits the 2V limit. Here an oscillograph with an output current of 70 A :

C1 (yellow) is the CS pin. C2 (purple) is Vout. C3 (light blue) is Drain of QD. C4 is OUTA from UCC28951. What do you suggest?

As a note, I've started this project with UCC28950, then I switch to UCC28951 hoping in a better behaviour near the current limit, but at this stage of development I'm not able to see any difference, maybe I'm doing something wrong.

Thank you

Hello,

Your inquiry has been received and it is under review.

Regards,

Hello,

The other option would have been to decrease Rt so the oscillator frequency was 90 kHz and sync to 200 kHz.

You may have been adding too much slope compensation.  The following link will bring you to an application note that shows how to design with the UCC28950 and the UCC28951.  There is section on how to setup the slope compensation.

https://www.ti.com/lit/pdf/slua560

Your current sense signal does look improved to what  you had before.  However, the slope of the CS signal is changing and looks to be saturating a little bit.  This possible could be cause if you add to much slope compensation the design could be running in voltage mode control.  Try adjust the slope compensation based on slua560 to see if the waveforms improve.

The UCC28951 was designed to operate at duty cycles greater than 90%.  From you waveforms it looks like it is the correct device for your design.

https://www.ti.com/lit/pdf/slua853

Regards,

Hi Mike,

I tried to increase the SYNC frequency as suggested. Nothing has change, The output is stable until around 20 A, but if I increase the load this is what the oscilloscope has recorded:

C1 (yellow) is the CS pin. C2 (purple) is Vout. C3 (light blue) is Drain of QD. C4 is OUTA from UCC28951. The quality of CS signal looks different because this record has been made with 1 s time division, and then zoomed in.

I'm not undestanding this point, see the red arrow:

It seems that UCC stops and restart, but the CS signal doesn't show an overcurrent prior to this point. The same board in master mode runs without any problem. I tried also to increase Rt to 82 K mantaining SYNC frequency 220 KHz, but without success.

If this condition persist, the UCC seems tro enter in Hiccup mode:

What do you suggest? 

Thank you

Hello,

Your inquiry is under review and I will get back to you shortly.

Regards,

Hello,

I took another look at the waveforms and at 1 out A turns on immediately after it turns off.  At this point the controller will demand 0% duty cycle which it does. 

At 2 Out A seems to be 180 degree phase shifts.  In the waveform below this happens 3 times.  Phase A should be synchronized to the mater clock and not be shifting. Could you double check that Out A in these waveforms is not OUT C or D?  Out C and D will phase shift based on duty cycle.

Would it be possible to retake this waveform moving the output to the sync pin?  I just want to see what the sync looks like relative to OUT A , CS and the QD drain. 

Regards,

Hi Mike,

Sure, see the folllowing oscillographs:

C1 (yellow) is the CS pin. C2 (purple) is OUTA. C3 (light blue) is Drain of QD. C4 is SYNC input.

Here the same anomaly recorded. Now more in detail:

From my point of view SYNC signal is stable, and the CS signal does not show an overcurrent condition. But it seems that UCC stops and then restart, causing now an over current condition maybe due to unbalancing of transfomer.

Here more in detail:

What do you think?

Thank you

Hello,

I just want to double check something.  When the device is working in slave (follower) mode to you have a 825 k ohm resistor tied from the SS pin to ground?

If not the device could misbehave when be synchronized.

Regards,

Hi Mike,

Yes I confirm the presence of the 825 K resistor in parallel to a 270 nF capacitor. 

I confirm also that I tried many times and this anomaly occurs always in the same way. 

Please let me know if you have any other question.

Thank you

Kind regards

Hello,

Your inquiry has been received and is under review.

Regards,

Hello,

Out A is going to track the sync signal with a slight delay produced by the clk.

Your waveform does synchronized and all of sudden there is a glitch on out A and Out A then turns on while Out C is high.  Please note QDd being high indicates out C is high.  This will cause 0% duty cycle which are you seeing by no presence of current on the CS pin right after the glitch.  During the switching period after the glitch the inductor current depletes to zero and gradually increases.  Out A is then synced however it was phase shifted 180 degrees before syncing up again.

I am puzzle why the current ramps up slowly after the glitch.  This has happened so fast the voltage amplifier should not have had time to change output voltage and the next switching cycle peak current should be controlled to the same amplitude not a lower one.

Even when I look at your waveform showing multiple behaviors the CS depletes to zero and then gradually ramps up.  It is almost when the glitch occurs the design is activating a soft start. Could there being something in your circuit that is causing a soft start?  You might want to check the voltage amplifier output and the SS pin during this behavior just to see if a start is being triggered. If the start is being triggered it could produce undesirable results.

You also may want to check VREF and VDD to make sure they have nice clean voltages and are properly bypassed with high frequency bypass capacitors.  If there is noise on these pins it could cause the controller to misbehave.

Regards,

Hi Mike,

Sorry for delayed reply, it has take a  while doing futher tests.

About your questions, in my circuit the soft start is controlled only by the capacitor on SS pin, and VDD and VREF are properly bypassed with 100 nF in parallel to a 1 uF capacitor, X7R.

Furthermore, in my circuit EA- and COMP pin are tied together, and the compensation network of the error amplifier  is connected to EA+.

Here some other oscillographs:

C1 (yellow) is CS pin, C2 (purple) is OUTA, C3 (light blue) is EA+, C4 (green) is SS pin. You can see that the compensation network is demanding higher duty cycle due to the voltage drop in consequence of the "stop" of the converter and the drop of primary current.

Here in a wider time:

And here the detail of the first "stop":

The compensation network is reacting maybe too fast, but this converter must have a very fast load transient response.

In my opinion this anomaly is not a soft start condition, which would be much slower: the current is rising in just 3 or 4 switching cycle, meanwhile the soft start controlled by SS capacitor require more than 200 ms.

Here the same behaviour with Vout on channel 4 (green):

Here VDD and VREF:

C1 (yellow) is CS pin, C2 (purple) is OUTA, C3 (light blue) is EA+ pin, C4 (green) is VDD 12 V.

C1 (yellow) is CS pin, C2 (purple) is OUTA, C3 (light blue) is EA+ pin, C4 (green) is VREF 5 V.

I have noticed that after the first anomaly the controller discharge slowly the SS pin  (C4, green) from 4.65 V to 3.7 V:

Following the datasheet, this means that the UCC is entering in cycle by cycle current limit:

And this is right, because this happens only after the excessive rising of the primary current after the anomaly on OUTA:

So, after those all measurements, I have not found an external reason that could bring the UCC to stop pulses on OUTA and then restart. Even the rising od EA+ voltage happens only after the anomaly condition. Moreover, the persist of this condition, as we have seen, bring to a transformer inbalance and then to HICUPP mode:

What do you think? 

I have read about the scope of the 825K resistor on SS pin, that is to prevent the UCC to enter in a "test mode", Could be there the problem? For some reasons it could be necessary to modify the value of this resistor? What does mean "test mode"?

Thank you very much.

Kind regards

Hello,

I am reviewing your inquiry and will get back to you shortly.

Regards,

Hello,

One other thing is puzzling to me.  When the misbehaver occurs inductor current goes from continues to to complete discharged.  You can observe this through the CS signal.  It is almost as if the load disappeared then comes back slowly.  Even with one cycle missed the DC output current should be present.  Your other waveforms shows that VOUT is not dropping enough to cause the load to start from 0 A.  Do you know what is causing this? 

This waveform that you show has the SS pin only go up to 3.8V.  Even with the 825 k ohm resistor to ground the capacitor should charge up to roughly 4.64V.  Is there anything on the SS pin besides the capacitor and the 825 ohm resistor?

C1 (yellow) is CS pin, C2 (purple) is OUTA, C3 (light blue) is EA+, C4 (green) is SS pin.

So it does not look like this behavior is triggered by an over current or resetting of soft start.  However, there is a lot of high frequency noise on all pins evaluated.  Is it possible that high frequency noise is triggering a sync of the master clock when it should not?  One thing you could try is adding RC filter from the sync signal to the Sync pin.  Try adding a 1k ohm 220 pF low pass filter between the sync signal and SYNC pin of the follower.  Put the capacitor as close to the SYNC pin and gnd pin of the follower controller as you can get it.  You also want the 1k ohm resistor as close to the sync pin as you can get it.  Keeping the traces as short as possible will reduce noise pickup from EMI antenna affect.

The 825 k ohm resistor is supposed to form a voltage divider with the 1 k ohm pull up resistor.  This should set the SS voltage to 4.64V roughly. I don't know what the test mode tests but it is suppose to be activated by pulling the SS pin above 4.95 V.  The resistor divider insures this does not occur.  It should need to be adjusted.  However, if you put to small of a resistor on the SS pin it can actually defeat the over current protection.

Regards,

Hi MIke,

I know that there are many high frequency noise in the oscillographs but my oscilloscope is off ground, and all the probes are grounded  in the same place near the DC power connector. Moreover, I don't use any filter, I'm trying to catching something of  unknow so I don't want to miss anythiing.

The SS pin is correctly charged to roughly 4.65 V from the start of the converter until this anomaly occurs. You can see this in the above oscillographs, see for example at this:

and here in a wider time:

You can see that the cursors on the C4 (green) trace shows a voltage of 4.62 V before the anomaly, then begin its discharge to roughly 3.8V. The strange thing is that even if I reduce the load, the SS pin is not pulled up anymore to 4.62 V until the next soft start (SS pin tied down to zero and then release). The datasheet seems to not saying too much about that.

In my circuit there is a Mosfet in parallel to the 825 K resistor and the Css capacitor. The Mosfet is controlled by an external circuit that disable the UCC if a fault condition occurs, but this is not the situation because in the above oscillographs the SS pin is not pulled down to roughly 0 Volts.

You are right that the inductor current starts from zero and as we have seen this is due to the moment in which the controller demands 0 duty cycle. The voltage drop is not so much, but there are 900 uF of total output capacitance. Looking at the above oscillographs there is a dropout of roughly 2 V in  roughly 32 uS, and that means a discharge curent of roughly 56 A, that is the load current at the moment of the anomaly.

Moreover, I use a DC regenerative electronic load, probably with a resistive load the load current itself would be more stable, but In my opinion this anomaly does not depends by the load (absence of overload condition).

Finally, about the SYNC signal, now I'm not using any filter, only a 47R series resistor with a 10 K pull down. This because the SYNC signal appears already filtered (the rising and falling front are already a bit rounded). In the above oscillographs the SYNC signal is stable and there isn't any sign of a glitch or something similar before and after the anomaly. The driving IC is a SN74LV244AQDGSRQ1. 

Moreover, I have already tried to adopt an RC filter (100 pF with 1 K resistor) but the result was getting worse, with the anomaly that occurs at lower load current. It seems that UCC needs fast transitions on SYNC pin.

Its many days that I'm working on this behaviour but still I'm not able to record something that could explain it. Is it possible to maybe think in the opposite side? From the point of view of the internal circuit of UCC, what could bring to this situation? Maybe there is something on the internal oscillator circuit that could explain something more.

Many thanks for your support.

Kind regards

Hello,

Only the AC current should go through the caps.  The DC current should come back as soon as the converter demands duty cycle.  It starting at 0 is not normal.  However, I think this has something to do with your load and not the anomaly.  You will have to check this out later.

If your design discharged the SS capacigtor to 3.8 V the cycle by cycle current limit of 2 V is being hit.  Even though this is not triggering a reset of a start it is happening.  This is most likely due not noise on the CS pin that can be reduced with a low pass similar to what I recommended for the sync pin.

Something in the design is triggering a reset of the sync.  I think it is noise.  In your system the SS of 3.8 V indicates the cycle by cycle peak current limit is being tripped, when it should not be. 

You did try the filtering the sync pin and you mentioned with a 1 k ohm, 100 pF capacitor and the issue got worse.  This filter would have a pole at 1.6 kHz and RC time constant of 100 ns.  I would not have thought this would not have made things worse.

The noise may be coupling in the CS pin.  Could try filtering that pin to see if it stops the SS pin from discharging.  Then see if it removed the anomaly?

Regards, 

Hi Mike,

Sure, I can try to over-filtering the CS pin and see what happens. Filtering too much the CS pin obviously implies that the peak current see from the UCC is lower than the real one, so the current at which the overcurrent limit is tripped will be much higher. This would probably not protect the converter in case of a real over current condition, for example transformer saturation.

Unfortunately, in the UCC design the maybe two most delicate pins (CS and SYNC) are one after the other (pin 15 and 16). For sure this doesn't facilitate the designers :-).

The fact that currents increase gradually after the anomaly could depends by the duty cycle being demanded by UCC?

Despite of all this, in my opinion, looking at the oscillographs, the SS pin being discharged from the UCC only after the anomaly occuring.

You can see it clearly here:

So in my opinion hitting the overcurrent condition is a consequence, not a cause of the anomaly. And it is real, as showed by the CS signal that after starting from zero ramps up very high toward the 2 V limit. So in this case is correct that  UCC begins to discharge SS pin.

What in my opinion is not correct is that the UCC produce this anomaly in outputs apparently without nothing causing it. Okay this could be due to noise, but looking at the documentation, noise on CS pin would bring to a limit on duty cycle, due to a premature trigger of the PWM comparator, and clearly this is not the case.

Effects on noise on SYNC are not well documented, but UCC should use the internal oscillator if SYNC remains to zero, and it should freeze the outputs if it remains high. Also here I think this is not the case.

What does you mean by "reset of SYNC"?  Can you explain the conditions in the SYNC signal that could bring to this behaviour? Do you mean the moment in which the UCC decide to use its internal oscillator despite of the external SYNC?

Thank you.

Kind regards

Hello,

This waveform shows the SS is at 3.8 V before the anomaly not afterword.  The only thing that is going to discharge the soft star capacitor is the cycle by cycle current limit, unless you have something else on the SS capacitor.

When the anomaly occurs the A output is shifted 180 degrees and stays that wat until the anomaly occurs again.  In this plot for the entire plot the SS capacitor voltage is 3.8 V.  Before this you mentioned it was the SS was 4.62 V.

I had recommended filtering because I thought noise was causing this.  You can do another experiment to see if it is in deed noise.

Run the device with input power applied to the power stage to see if the synchronization is lost.

Regards,

Hi Mike,

Sorry maybe I have not been enough clear. I think that this is a very important point so please trust me. As I have descrived  above, and as I have showed you on the waveforms, SS pin is correctly  pulled up at 4.62 V at the momnt of the first occuring of the anomaly:

Then the SS pin is discharged by the UCC, here you can see clearly its discharging:

Then, if I decrease the load current, UCC returns to work normally, but if I increase again until the same load that causes the first anomaly, the same behaviour occurs. The difference, and probably this is what is confusing you, is that the SS pin is never pulled up again by the UCC, even if the load current decrease and trhe normal functionalities are restored. 

Is that correct?

So -  the SS pin is discharged only after the first anomaly occurs, the ocillograph that you show in your last reply simply has been taken without power OFF and the ON the converter after the first anomaly.

Please can you share your thoughts about the questions of my last reply? Maybe they woulld be useful to understand more how the internal oscillator works with SYNC.

Thank you

Kind regards

Hello,

I have received your inquiry and this is under review.

Regards,

Hello,

I read through the thread and the question is in regards to the sync function.

The sync occurs on the trailing edge of the sync pulse.   The below snippet from the data sheet show output A and B vs the sync signal.

The waveform below you took previously.  CH1 is CS, CH2 is out A and CH4 is the sync pulse.  CH3. The issue is when the anomaly/glitch occurs the sync seems to change.  I drew on the waveform in white where out A and Out D should be if synchronization was not changed.  It is as if the devices out A's sync has changed after the anomaly. It looks like the outputs are resynchronized at the glitch between the two out As being high, with a glitch inbetween. 

I think you have noise in the system that is resyncing your outputs causing this issue.  This is why I made the recommendations that I have. 

Regards,

Mike