Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC5880-Q1: Power-up failure at high temperature

Part Number: UCC5880-Q1
Other Parts Discussed in Thread: UCC5880QEVM-057, UCC14240-Q1

We've run thermal tests at tempeature (over 100 degC) on the UCC5880QEVM-057 and we're having issues with communicating with the UCC5880-Q1 devices after a power-cycle. 

When we power-up the devices at 25 degC and then ramp up the thermal chamber to around 110degC ambient, we have no issues communicating over SPI (with no indication of faults).  When we power cycle the devices at 110 degC, both nFLT outputs are asserted (low) and we are unable to establish communications over SPI.  We have confirmed that the secondary-side power supplies are up and running.

Is there any particular reason for this bevaviour given the device is rated for up to 125 degC?

  • Hi Steve,

    Just to make sure I understand, when you power up at 25C and then ramp up to 110, you have no issues. However, when the thermal chamber is already at 110C and you try to power up the device it doesn't work correct?

    SPI will not function without the primary side supply. Can you make sure to check that the primary supply voltage is working correctly? Can you also share the voltage and current draw for the primary and secondary side supplies for the EVM?

    What do you mean by you cannot establish the communication? Are you unable to read or write to the device? Can you try to read the faults?

    Regards,

    Akshat

  • Hi Akshat,

    Your understanding is correct Thumbsup.  The issue arises when the thermal chamber is already at 110 degC and we then attempt to power-up the devices.

    We've confirmed that both the primary and secondary side supplies are operating at their nominal voltage levels (I don't have the exact current values unfortunately so will have to get back to you in this regard).  We were conscious that the power-supply ICs (UCC14240-Q1) have their own requirement of their junction temperature being below 130 degC in order to power-up, so we have made sure that the secondary supplies are operating.

    Just to clarify on the communication, we send a command over SPI to the Gate Driver ICs but receive no response, so consequently we are not able to read the fault registers.  I would expect to be able to read registers in the event of an ABIST failure (which I think is being indicated by both nFLT signals) but I suspect that there is another fault at play that is preventing us from reading any registers over SPI.  I haven't yet confirmed that we cannot write registers, but I imagine the best way to do this (withouth being able to read SPI) is by changing the configuration so that the change can be visible from other I/O.

    Best regards,

    Steve

  • Hi Steve,

    Understood, thanks for the clarification! 

    Are you using our GUI? If so, you can check if the MCU or EVM is communicating and still connected through the GUI menu.

    The faults that could cause the SPI to not be read are any OV/UV conditions or internal regulation issues. Any noise in the system may also couple into the internal communication lanes and cause this. I have some suggestions below to understand this better.

    Once this fault occurs and SPI cannot be read, can you try to ramp it back down to ambient temperature? If the high temperature is causing any regulation issues, lowering down should make it recover. Once the power recovers, SPI should be enabled again.

    Can you also try to probe the SPI signals? This will help is understand if the driver is able to receive and send out signals correctly.

    Regards,

    Akshat

  • Hi Akshat,

    Thank you for your patience, we were not using the GUI, but instead our own SPI communications.  We found that when the IC enters this faulted state at high temperature, it did not recover when the chamber temperature was brought back down to ambient.  It was only upon a power-cycle were the ICs able to recover.

    After extra testing, we have found that increasing the slew-rate of the external power supply allowed for the gate driver ICs to initialse correctly (so we can now talk to it) and with no faults.  Is there a requirement for the minimum slew-rate for VCC1 so that the IC can power-up correctly?

    Regards.

    Steve

  • Hi Steve,

    Glad to know you were able to establish communication. We only spec a maximum slew rate of 0.1V/us for the supplies. The SPI will not work unless the VCC1 will go above the VCC1 UVLO. It looks like due to the temperature in thermal chamber, the VCC1 supply was not able to source enough current to make the VCC1 reach the correct voltage. Another reason is that the VCC1 is unable to reach the required voltage level before ABIST happens or before the internal regulators have received power and somehow the temperature is affecting this. 

    As long as the slew rate is under 0.1V/us, you should have no issues.

    Regards,

    Akshat