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TPS2HCS10-Q1: SPI interface protocol

Part Number: TPS2HCS10-Q1

Hi team,

I have a question about SPI protocol of TPS2HCS10.

It is described in the draft datasheet that the data written to the register is updated on /CS rising edge 

and read clear register is also cleared at /CS rising edge. 

"Rising edge on the CS pin initiate following actions:
1. Addressed registers are updated if there is no SPI communication error and if it is an SPI write command.
2. Read clear register is cleared if a READ command to this register was issued during CS = LOW."

Q1. If I send 2 commands while /CS holding Low, both of the commands are received and updated at next /CS rising edge? 

Or the later command only received and updated? 

Q2. How long does it take to transition to SLEEP state after I send SLEEP SPI command at ACTIVE state?

Q3. I plan to turn off VDD after the device go into SLEEP state. How long should I wait after I send SLEEP SPI command to the device?

regards,