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BQ40Z50: Preventing excessive battery discharge in different scenarios.

Ian Aherne
Prodigy 200 points
Part Number: BQ40Z50

Hi 

We are using the BQ40Z50 in an application where we have 3 possible scenarios for battery discharge

1: The battery can be discharged very slowly if left in storage for very long periods of time (weeks) DSG FET off NR = 0

2: The battery pack can be discharged slowly if left idle for long periods of time.(Hours) DSG FET on.

3: The battery pack can discharge quickly when in in active use under high loads (minutes) DSG FET on.

Ideally we don't want the cells to discharge below 3 volts when in any mode. 

A 3V CUV threshold causes issues when the device is in active mode under high load because the voltage can drop well below that threshold for periods of time but the voltage will bounce back when the load is stopped..

Reading the TRM it seems the CUV or CUVC are the only way to terminate discharge while staying in active mode is this correct? 

I would like some advice on how to set the thresholds so they will work for scenario 2 and 3. 

I would also like some advice on the best approach to minimize further discharge in scenario 1 when the DSG FET is already off.

Regards

Ian

  • 0
    TI__Mastermind 25835 points

    Hi Ian,

    You can put the device in sleep mode for scenario 1.

    Please allow me sometime to align with my team on the best way to approach your application.

    Regards,

    Evan

  • 0 in reply to Diego
    TI__Mastermind 25835 points

    Hi Ian,

    Sorry for the delay.

    Once CUV threshold is reached the FETs will open, which should be ok for scenario 2.

    For scenario 3 you will need to adjust the CUV delay.

    Regards,

    Evan

  • 0 in reply to Diego
    Prodigy 200 points

    Thanks Evan

    yes this is what I have done in my configuration and you have confirmed for me that this is the correct approach.

    The reason I asked is because it seemed strange that there is no configuration option to switch off the DSG FET on setting of the TD bit, especially when there is an option to do this in charge mode using the TC/CHGFET bits. 

    Is there a reason for this?

    Regards

    Ian