BQ40Z50-R2: The firmware version is 4500_2_11

Hello,

We would recommend following the layout recommendations in Section 11 of the bq40z50 datasheet to help mitigate the effects of ESD and EMI on the device.

We can also take a look at the layout of the design and give recommendations if the files are shared.

Regards,

Anthony Baldino

I used the EVM board to verify whether there was false current under the 2.4G WIFI signal, and the result was also false current. Is it possible to explain that the EVM PCB design does not prevent the generation of false currents? The EVM plate is designed with differential surface covering. Can the differential full coverage ground method further reduce the crosstalk from the 2.4G WIFI signal to the current acquisition?

Which approach is better for reducing crosstalk by bringing two differential acquisition lines closer together or using a fully covered ground for each differential acquisition line?

Hello,

The EVM design is typically not built to handle high levels of EMI, and is for evaluation purposes only. Can you tell me what the value of the false current is? If the value is low enough then the Deadband parameter can be changed to accommodate this.

Regards,

Anthony Baldino  

I designed the PCB by myself, under 2·4G WIFI signal, the maximum false current reached more than 200mA. Using EVM board test under 2·4G WIFI signal, the maximum false current reaches 30mA. I urgently need a suggestion to reduce signal crosstalk, and I want TI's technical experts to guide me on how to rectify it.

There is no false current under the 5G WIFI signal, and only the 2·4G signal exists.

I wonder which approach would be better to reduce crosstalk, stick the two differential acquisition lines closer together, or use a full-coverage grounding design for each differential acquisition line.

Hello,

When you say full coverage grounding design, are you talking about the introduction of a ground plane to the PCB stack up? If so, we would recommend doing that for the mitigation of EMI. 

I will reach out to our hardware team to see if they have any input regarding this issue.

Regards,

Anthony Baldino

Hello:
My PCB design is two-layer, different from the 4-layer design of the EVM board, mainly considering the cost factor. The layout of the double-layer PCB cannot achieve a complete connection plane in the inner layer. The current differential acquisition design is shown in the PCB screenshot above. The left and right sides of the current differential collection line are grounded to the next layer, that is, three sides of the differential collection line are surrounded by ground, may I ask whether such a design has an effect on reducing EMI.

Hello,

To better my understanding of this issue, the green layer in the image above is the top layer with all the red circles around it being vias to the bottom layer?

I have reached out to our hardware team to get there insight to this issue. I will send an update tomorrow.

Regards,

Anthony Baldino 

Yes, the green is the top layer, the blue is the bottom layer, and the red circle is the through hole, connecting the bottom layer and the top layer.

Hello,

I have received an update from our hardware team, and they believe that the only improvements to this layout that might assist the reduction of EMI are to remove the ground line between SRP/SRN and route them adjacently the entire way to the sense resistor. Also, moving the sense resistor closer to the device could assist, however it looks like space is limited in the screenshot above.

I see in that video above that the false current is roughly 8mA, are there any issues occurring with the gauging accuracy?

Regards,

Anthony Baldino