TPS6594-Q1: What is ERR_AP_PMIC_BUCK_LDO_OVI?

Hello Sung,

Can you please explain again where or what registers are you seeing this error as I do not see this field name for errors in our datasheet or User's guides.

BR,

Nicholas

Dear Nicholas,  

We are using the AP_PMIC(LEO-A) buck output 3-phase(buck 1,2 & 3) and set the BUCK1(2,3)_ILIM 5.5A 

When TDA4V run at full-load, LEO-A has value 0x80 or 0x88 at addr 0x5C 

It means, PMIC Buck 1, 2 current limit has been triggred 

We found about PMIC buck current limit issue in e2e system, it is very silimar us case, but the soultion does not share

This issue occured about 1 year ago, i think you know the solution 

Would you tell me solution? 

(+) TPS6594-Q1: TPS6594-Q1 report current limit alert on Buck 1&2&3 output (VDD_CPU_AVS) - Power management forum - Power management - TI E2E support forums

Thanks 

Sung mo jung 

Hello Sung,

Jung sungmo said:

We found about PMIC buck current limit issue in e2e system, it is very silimar us case, but the soultion does not share

I'm assuming you have tried to set BUCK1_FPWM_MP bit to 1?

Any other solutions you have tried yet?

In the meantime to cut down on the solution time, could you provide me with the schematic relating to the BUCK1, BUCK2, BUCK3?

I will be speaking with my team on this matter,

Thank you & BR,

Nicholas

Dear Nicholas 

We don`t try other solution yet, (including BUCK1_FPWM_MP)

We are using the BUCK1, 2, 3 3Phase. 

Even though Buck4, Buck5 are different power rail, Is there any problem if i change the BUCK1_FPWM MP bit to 1? 

I attached the schematic 

Capacitance of VDD_CPU_AVS rail has 47uF * 10, 22uF * 1 and 10uF *1

Would you let me know if your team has found a solution to this problem?

Thank you 

sung mo jung 

Hello Nicholas,

This is Jisung, a colleague of Mr. Jung, who is mentioned in the question you received.

I'd like to provide further information regarding this issue.

Actually, this system has been designed based on T.I.'s recommended PDN, as shown in the table below.

If the "Output current capacity" is under peak current conditions, there is a high probability that an overcurrent warning will occur in an AVS operating environment when full load is applied.

This is critical issue that infront of mass production, Please check quickly and with deep interest.

Thanks, Regards.

Dear Nicholas 

I measured PMIC Buck 1,2,3 current and switching waveform at SW full load condition 

I hope this waveform will help your solve the issue.

Thanks 

Sung mo jung

Hello Sung,

So, only do BUCK1_FPWM_MP as this is the main buck control for the ones in multiphase. Please try this.

Also, please do no place BUCK4 or BUCK5 in forced multiphase PWM.

Hello Jisung,

Jisung Hyun said:

If the "Output current capacity" is under peak current conditions, there is a high probability that an overcurrent warning will occur in an AVS operating environment when full load is applied.

This is critical issue that infront of mass production, Please check quickly and with deep interest.

I understand, but the PDN-0C was/is tested for the maximum output.

Sung, Jisung,

Layout has a critical impact on the performance of the BUCKs in multiphase both in current and voltage. Can you double check if the feedback pins for the FB_B1 & FB_B2 are differentially routed as well as trying the above of forcing it in PWM.

If possible can you send the layout files to review over a direct message or over email: n-mcnamara@ti.com

These screenshots look very similar to something we've seen before regarding the layout, placement of feedback traces are key.

BR,

Nicholas

Hello Nicholas 

I sent you the pcb file via email, please check it.

We modified BUCK1_FPWM_MP bit 0 -> 1, and ERR_AP_PMIC_BUCK_LDO_OVI did not appear.
So we measured the BUCK1 current but the maximum still triggered at 5.5A.
However, there was a slight reduction in peak current when changing bit 0 -> 1, but it is difficult to judge as a solution
Because, when operating at high temperatures, current consumption will increase due to heat, and then the current limit will operate in the same way.

We want a way to lower the peak current.

Thank you,  

Sungmo.jung 

Hello Sung,

Thank you for the feedback.

I will be looking at the layout and will reply in the email.

BR,

Nicholas

Hello Nicholas, 

We are waiting for the result of the PCB review and the solution. 

Additionally when changing BUCK1_FPWM_MP bit 0 -> 1, the peak current is reduced by about 200~300mA. 

However, under this condition, it reoccurs at a high temp of 65℃ 

Thanks 

Sung mo jung 

Hello Sungmo,

I have replied to the email, please see the comments.

BR,

Nicholas

Hello Nicholas 

It looks like it was reviewed with a different PCB file.
The feedback pin is differentially connected to the point of load.

Please check again and reply to the inquiry email.

Thank you 

sungmo jung

Hello Sungmo,

responded in the email.

BR,

Nicholas

Hi

expert.

If I ignore error message of pmic oc protection, which side effects exist?

and after oc protection alert, does PMIC have another action to protect system?

I'm warried about chip damage after I block oc protection alert. 

Thank you.

Hello Sungmo, Youngwoo,

The masking of the ILM (or current limit) will not remove the protection in place, the device has a hardware monitoring in the case of hardware limited current delivery (excessive heat, excessive current to destroy device, etc..)

youngwoo lee said:

If I ignore error message of pmic oc protection, which side effects exist?

and after oc protection alert, does PMIC have another action to protect system?

As noted above there is a fallback system, and the side effect is that earlier onset warnings will not trigger the interrupt pin to signal this.

The device will not allow for an excessive pull on the system and will power off if this hard limit is reached.

BR,

Nicholas

Hi

I have a few additional questions.

1. Can I know why PMIC is power off? ex) read registor?

2. I'd like to know current limit value of protection when PMIC is turned off.

Thank you.

Hello Nicholas 

I'm inquiring about the over current issue because I need to check the validity of the HW design.

PCB Review result :

1) There is not problem about FB_Bx pin routing(as Pseudo differential pair)

2) Designed with 4 mil FB_Bx pin. (6 mil recommended)

Inquiry

1. Please explain the reason for the design of FB_Bx pin at least 6 mil.

2. Please know about the current consumption of FB_B1 pin 

3. It has 140 mA allowable current when it is PCB Trace Width 4 mil(based on IPC-2221). FB_BX pin has a sense function, however it requires a lot of current, so is it minimum 6 mils specification?

IPC-2221 allowable current calculation 
The CircuitCalculator.com Blog » PCB Trace Width Calculator

Thank you, 

Sung mo 

Hello Mr. Lee,

youngwoo lee said:

1. Can I know why PMIC is power off? ex) read registor?

If the VCCA, VIO, I2C pull ups are available you can read the registers 0x5A - 0x6C. In the datasheet these interrupts will explain the errors.

In this case, the current limit is the problem.

youngwoo lee said:

2. I'd like to know current limit value of protection when PMIC is turned off.

The current limit shutdown is an active protection if the PMIC has no power, VCCA == 0V, there's no current going through the device hence no need for the protection. When powered there is always a hard current limit protection in place on the BUCK outputs.

BR,

Nicholas

HI 

Nicholas McNamara said:

When powered there is always a hard current limit protection in place on the BUCK outputs.

I want to know "hard current limit" value. ex) 1A? 500mA?

Thank you.

hi

Nicholas McNamara said:

If the VCCA, VIO, I2C pull ups are available you can read the registers 0x5A - 0x6C. In the datasheet these interrupts will explain the errors.

When PMIC restarts can I read error registors? Are error interrupt registors volatile? 

Thank you.

Hello Nicholas McNamara

Please check Jung sungmo's Question about the current requirement of FB_B1 pin.

Thanks.

Hello Sung Mo,

Jung sungmo said:

3. It has 140 mA allowable current when it is PCB Trace Width 4 mil(based on IPC-2221). FB_BX pin has a sense function, however it requires a lot of current, so is it minimum 6 mils specification?

6mil is based upon the analog designers and with our schematic/layout checklist to account for fluctuations in temperature and other factors to get the most accurate feedback in all conditions.

BR,

Nicholas

Hello Youngwoo,

The hard current limit is based from the forward current limit from the datasheet. Now this is for the accuracy, so this 5.5A has variations.

BR,

Nicholas

Youngwoo,

youngwoo lee said:

When PMIC restarts can I read error registors? Are error interrupt registors volatile? 

In the case of a shutdown that is cause by error in the output (current limit, short circuit, over/under voltage), the device will either fall back to another state or restart, yes the registers can be read, if the VCCA, VIO_IN, pullup resistors for I2C are on.

They are volatile, they will go away when the VCCA go below the voltage needed to keep the digital alive (2V75~)

BR,

Nicholas

Hello Nicholas 

When the TPS6594 Buck1 is a current limit(5.5A) condition, i`d like to know the time from internal FET turn off to turn on

Thanks, 

sungmo 

Hello Jung Sungmo,

From the datasheet, as it varies due to switching frequency, but the expectation of 30us:

BR,

Nicholas