LM51521-Q1: Layout review

Hi Jeff,

Sorry for the delay here is what I have got:

- The CSN and CSP lines are crossing the Q2 FET, this can be not very desirable as there might be noise pickup from Q2 to the current sense lines, but there is a ground plane between them so it should be ok, but just as a rule it is best to avoid this. Also, C536 should be as close to the IC as possible, in the layout I can see it can be placed closer to the IC.

- The output capacitors are shared between the boost mode when current goes through Q2 of high side FET and bypass mode when the diode D1 is passing the current, could be problematic as I see ceramic being used only for boost mode and electrolytic for the other, this is in general not a good practice, as far as I know.

-HO pin (pin 5 of the IC) is thinner at the beginning, it should be as thick as possible as this is the gate driving pin.

-RT pins resistor R536 should be closer to the IC.

- AGND should be separate from PGND and should have just a small net connecting them together instead of being the same. There are some sensitive parts of the IC connected to AGND, that could pickup noise from PGND, which could come from the SW node or power stage.

Hope this helps.

BR,

Haroon