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TIDA-050063: The design guide gives strange information on how to select C_DIV1 and C_DIV2 for TPSI3052-Q1.

Emil Tagesson
Prodigy 20 points
Part Number: TIDA-050063
Other Parts Discussed in Thread: TPSI3052-Q1

Hello,

I'm developing a precharge solution using your TIDA-050063 Design guide. 

I am a bit confused about the gate driving circuit. Specifically TPSI3052-Q1.
For the selection of C_DIV1 and C_DIV2 it is stated that higher values = less VDDH drop, but slower turn-on time. 
Then you say that: "The MOSFETs selected for this design each have a gate charge (QG) of 55-nC" on page 11. The TPSI3052-Q1 is not driving any mosfet, it is supplying the mosfet lowside driver UCC27517AQDBVRQ1 with power. You then recommend we use an excel calculator to select these capacitances but that seems strange since it's not adapted for driving a IC. My selected mosfet has a Ciss of 1100pF but I don't see it as relevant since we want TPSI3052-Q1 to just be a reliable power source. This would mean that having high values of C_DIV1 and C_DIV2 is preferable since we won't be doing any switching with TPSI3052-Q1. Could you clarify how C_DIV1 and C_DIV2 should be selected for the reference design? 


Best,

Emil

  • 0
    TI__Expert 5536 points

    Hello Emil,

    Thanks for joining E2E and reaching out to our team! I agree that this portion is confusing for how CDIVx is relevant when the TPSI3052-Q1 is not directly driving the MOSFET but providing power to the UCC gate driver. So this begs the question, how is the UCC gate driver driving the MOSFET? The UCC gate driver sources current from its VDD pin, which is supplied by the TPSI3052-Q1. So the TPSI3052-Q1 is indirectly driving the MOSFET. I think of the UCC gate driver effectively as an AND-gate with a small quiescent current (looks like max 0.160-mA), ANDing the outputs from the TPSI3052-Q1 and the hysteresis circuit. 

    So CDIVx must be sized appropriately to support switching a given MOSFET so that the gate voltage does not droop below what is desired (typically Miller plateau). High CDIVx values may not always be desirable given timing constraints (e.g. need to complete 99% pre-charge within 400-ms) since on power-up, CDIVx capacitors must charge above UVLO thresholds before any switching can be done. 

    When modifying this circuit and trying to account for the TPSI3052-Q1 power transfer limitations, it is important to consider:

    • MOSFET total gate charge (Qg)
    • Maximum switching frequency (Fsw_max)
    • Hysteresis resistors: constant current consumption

    All these factors can be input into the Excel calculator tool (SLVRBI9) to verify functionality during development. 

    Best regards,
    Tilden Chen

    Solid State Relays | Applications Engineer