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TLV1117LV: Latched high passive current consumption when switching from back-powering LDO to forward-powering

Part Number: TLV1117LV
Other Parts Discussed in Thread: TLV1117

Hi everyone, first time posting on this forum.

We have had strange issues with this device in our PCB designs and I have managed to recreate the strange behaviour with a simple setup for this post.

The summary of the issue is that the device can end up in a "latched" state where it draws ~200mA @ 5V and gets very hot, even with no output load. This state does not go away until the 5V is removed and then reapplied, at which point the device runs cold indefinitely. The state is entered if the device was being back-powered (i.e. the LDO output rail is still present) when the supply is enabled.

The following steps can be done to reproduce this issue:

  • Set up TLV1117LV33 with 1uF input and output ceramic capacitors
  • Apply 3.3V to the TLV output pin
  • Temporarily load the TLV input pin (I drew 200mA to GND for ~100ms)
  • Apply 5V to the TLV input pin

After this the device consumes ~200mA with no load until the power is removed and reapplied. This has been tested on multiple brand new devices.

Any clue what could be going on? It does not happen with other 1117 regulators.

  • Hi Phil,

    When you reverse bias an LDO by applying voltage to Vout without voltage on Vin, you forward bias the internal pass device body diode.  In this mode the internal temperature protection is not active, as well as other protection features such as current limit.  See this text in page 11 of the datasheet:

    "The PMOS pass transistor in the TLV1117LV has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited; if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended."

    Applying voltage on Vout that is higher than Vin is outside of the intended application of the TLV1117LV and we do not have data characterizing the LDO in this mode of operation.  I recommend limiting the reverse current to no more than 5% of the rated current draw which for this device is 50mA.



  • Hi Stephen,

    I completely understand this and had read this section of the datasheet in detail. However, this "deep dive" into the regulator's "latch" behaviour was triggered by the regulator going into "latch" mode simply from the inrush of capacitors on either side of the regulator.

    It should not be possible for 1117 devices to sink >200mA into their GND pin whilst the input and output voltages are within the device's allowed ranges IMO. I am trying to work out if the device series is flawed or if the devices I purchased are from a bad batch.

  • Hi Phil,

    I'm unsure if I understand the phrase "inrush of capacitors on either side of the regulator". In general, operating an LDO where Vout > Vin is beyond the intended operation of the device and at a minimum we recommend limiting the reverse current to 5% or less of the rated LDO current.  As mentioned, we don't have this LDO characterized when Vout > Vin. Typically, the TLV1117 has an application circuit where reverse current is handled via an external anti-parallel diode from Vout to Vin.  The TLV1117LV does not have this application circuit, however the TLV1117 datasheet shows this (figure 8-1 in the datasheet linked below), as do other LDO's.

    If you have an application where Vout > Vin then we recommend an LDO with reverse current protection so you do not need to add this external schottky diode.  Let me know your output current needs and any other important requirements you have not already listed in this E2E thread, and I can get back to you with some suggested options.