UCC28070: interleaved pfc

Hello Nithin, 

Thank you for your interest in the UCC28070 PFC controller. 

The UCC28070 uses average current-mode control to shape the inductor current to match the input voltage waveform.
Average current-mode control requires sampling the full, complete inductor current during each switching cycle.

Direct resistive sensing of inductor current in a high-power PFC can be very lossy, so a current-sense transformer (CT) can be used to scale down the inductor current much lower and significantly reduce dissipation in the current-sense resistor.  However, continuous inductor current would saturate the CT, so ordinarily two CTs are used, one in the main switch path and one in the output diode path.

The main switch current is the rising current in the inductor and the diode current is the falling current in the inductor. The outputs of the two CTs are summed together to obtain the complete inductor current, bit rising and falling portions.  The switch CT can be reset while the diode is conducting, and the diode CT can be reset while the switch is conducting. 

However, this method requires two CTs per inductor and the UCC28070 controls interleaved phases so there would be 4 CTs total in a design.  The CT approach might become a bit expensive.  Using current-synthesis, the UCC28070 can eliminate the requirement for CTs in the diode path.  The switch CTs generate the rising current signals into the CSA and CSB inputs, and the internal synthesis circuits emulate the falling current slopes when the switch current is off.

The total inductor current is emulated within the IC by using only the rising current signal.  This process is described in the UCC28070 datasheet in Section 7.3.8 (page 19). 

A resistor on the RSYNTH input of the IC is used to program the down-slope of the internal emulated falling signal.  The value of the resistor is calculated using equation (12), shown within that section of the datasheet.  During the switch on-time, the CT generates a rising voltage signal that corresponds to the rising inductor current.  During the off-time, the synthesizer generates a falling voltage signal by discharging an internal capacitor with a current proportional to that programmed by Rsyn.  The correct value of Rsyn results in the correct falling slope of the synthesized current so that the total current signal to the current amplifier input is the same as if two CTs had been used to sense the full inductor current. 

Incorrect values of Rsyn would result in a down-slope that is either too steep or too shallow compared to the actual current slope, and that would increase distortion of the PFC input current.  The result of equation (12) should provide the correct value for Rsyn, provided that the inputs to equation (12) are accurate. 

Regards,
Ulrich