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BQ25792: BQ & inductor placement at PCB

Björn Hellerstedt
Prodigy 190 points
Part Number: BQ25792
Other Parts Discussed in Thread: BQ25790

Hello 

I just want to confirm. This is a prototype going to production soon.

See screendump below. L600 is the inductor, U600 is BQ25792.

U600 and L600 is placed at bottom layer. 

Blue area is the switch node and placed at L3-Sig. Layer up is L2-gnd Solid plane GND. Layer below is L4-pwr this is 3.3V ( processor voltage ) solid layer.

Is this a good layer to place the switch node conductors? Else only alternative is bottom side ( same as component U600 & L600). 

Any risk to cause noise at 3.3V plane?

Please let me know your thoughts.

Thank you so much for your help!!

  • 0
    TI__Guru**** 165986 points

    Hi Bjorn,

    We generally recommend, IC on top, GND on 2nd, SW traces on 3rd and then another GND on 4th if possible.  Please flip those PMID and SYS 0.1uF capacitors around so that they connect to IC GND pin on top layer.  If not, the switching noise in the current sense amps will power limit your converter.  The datasheet recommended layout is below.  Bulk caps do not necessarily need to be that close to IC on top layer but fewer vias result in lowest output voltage ripple and best transient response.

    Regards,

    Jeff

  • 0 in reply to Jeff F
    Prodigy 190 points

    Hello Jeff

    Thanks,

    To be clear. U600 and L600 are mounted on BT side on this brd. 

    I guess you mean capacitors, U600 and L600 chould be on the same side?

    Same with 0.1u for PMID and SYS

    C618 is 0.1uF SYS cap.

    C614 and 6161 10uF sys cap 

    C619 is 0.1uF PMID cap. 

    C615 and C617 10uF PMID cap.

    On TOP side there are additional 10uF cap for SYS and PMID I had to do this because of space...

    This is BT side and flipped ( no mirror-view)

    I guess the only drawback is we don't have GND plane on L4 it is 3.3V power plane but I guess return current at high f will only be in that area where the sw traces are ( eddie current )? any other drawbacks?

    Thanks, 

  • 0 in reply to Björn Hellerstedt
    TI__Guru**** 165986 points

    Hi Bjorn,

    The inductor can be on either side.  The 0.1uF capacitors must be on same side as IC without vias connecting to PMID and SYS and GND pins.  With first internal layer from IC not being ground, there will be more resistance on ground return so I recommend adding as many GND vias as possible.

    Regards,

    Jeff

  • 0 in reply to Jeff F
    Prodigy 190 points

    Hello Jeff

    I dont understand your answer. 

    The 0.1uF caps are on the same side as U600 ( BQ25792 ). I have marked them at picture below. They are all placed at Bottom ( L8 ).

    First layer from IC is GND ( L7-GND ). This is for return GND current. ok?

    See my first question:

    Blue area is the switch node and placed at L3-Sig. Layer up is L2-gnd Solid plane GND. Layer below is L4-pwr this is 3.3V ( processor voltage ) solid layer.

    Question is, do you recommend a GND shape area at L4-pwr below the switch node traces or should I leave it as it is?

    Thanks

  • 0 in reply to Björn Hellerstedt
    TI__Guru**** 165986 points

    Hi Bjorn,

    Ground return is ok.  In general, placing ground directly under SW node creates a capacitor that spews EMI.  We typically do not place GND under the SW nodes.

    Regards,

    Jeff

  • 0 in reply to Jeff F
    Prodigy 190 points

    Hello Jeff

    Not sure about your answer.  "in general, placing ground directly under SW node creates a capacitor that spews EMI.  We typically do not place GND under the SW nodes."

    In your previous answer:

    "We generally recommend, IC on top, GND on 2nd, SW traces on 3rd and then another GND on 4th if possible.  "

    Not sure what you mean this time..

  • +1 in reply to Björn Hellerstedt
    TI__Guru**** 165986 points

    Hi Bjorn,

    EVM top layer

    Bottom layer with ground copper cutout highlighted

    Internal layer 1 ideally would have had a bigger cutout

    Regards,

    Jeff

  • 0 in reply to Jeff F
    Prodigy 190 points

    Hello Jeff,

    If I look at PCB for BQ25790 ( BMS027A ) there is no cu cut anywhere.

    GND layer on BT and L1, SW traces are at L2. 

    I think this is the most common way to do this. 

    I did a comparison between BMS034A and BMS027A with EMI sniffer to spectrum analyzer on both sides of PCB. I can't see any significant difference at all between the boards. DUT: Vin 5v, 2S Li-Ion chg 1A, 22 ohm load to Vsys.

  • 0 in reply to Björn Hellerstedt
    TI__Guru**** 165986 points

    Hi Bjorn,

    Ok.  If your data doesn't show EMI, then pour ground under the inductor.

    Regards,

    Jeff