TPS548D22: about FSEL register

user1972741 

user1972741 said:

Could you please tell me about RCSP_FSEL[1:0] in the settings determined by FSEL register?

RCSP_FSEL[1:0] is bits [3:2] from the decoding of the resistor divider connected to the FSEL pin.

user1972741 said:

What are you configuring on TPS548D22?

RCSP_FSEL[1:0] along with the frequency selected by FSEL[1:0] selects the internal ramp time-constant used by the internal D-CAP3 control loop to add in-phase ramp to the feedback to stabilize the constant on-time (COT).

user1972741 said:

It seems that the [internal ramp amplitude] is set, but please tell me how to determine the appropriate value.

Yes, this is the internal ramp amplitude.

A higher ramp amplitude (lower R, smaller ramp time-constant) will produce less switching frequency jitter and require less output capacitance to meet stability requirements, but will respond more slowly to a load transient.

A lower ramp amplitude (higher R, larger ramp time-constant) will produce more switching frequency jitter and require more output capacitance to meet stability requirements but will respond more quickly to a load transient.

Table 7 on page 25 in the datasheet provides general recommendations for the ramp option given the output voltage range, and also provides the time-constant selected with each ramp option.

Alternately, you can estimate the RSP to IL forward transconductance of the TPS548D22 by 8 x tau / L where:

tau is the time-constant of the ramp selected

L is the inductor value

The peak dynamic output impedance of the closed loop converter is Vout / Vrsp x L / (8 x tau) and the output capacitors should have an impedance less than or equal to that value for all frequencies greater than Fsw / 4.

user1972741 

You're most welcome.  Since this has resolved your issue, I will close out this thread.  If you have other questions or issues, please "Ask a new question"