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LM5152-Q1: LM5152QRGRRQ1　simulation model

teruyoshi takahashi
Prodigy 50 points
Part Number: LM5152-Q1
Other Parts Discussed in Thread: CSD18540Q5B, LM5152EVM-BST

Hello

Please tell me about the simulation model (transient) of LM5152-Q1.

The description of the model's application note includes the following statement.

2. The test bench is set at VIN = 5V, VOUT = 10V, Iout = 5A.

Does this mean that this setting cannot be changed?

For example, is it possible to stably output VIN from 6.5V to 12V, VOUT to 12.5V, and Iout to 9A?

4. The following features are not modeled

a. clock synchronization

b. Clock dithering

c. Switching frequency program by RT.

Enter the desired switching frequency (FSW) in the script window (F11).

Does the fact that this is not modeled mean that synchronization with FPMW mode or external clock is not possible?

Also, although the model does not have an RT pin, does this mean that the corrections will be applied automatically if you input an external clock?

Best regards,

takahashi

  • 0
    TI__Mastermind 19625 points

    Hello Takahashi-san,

    Thanks for reaching out to us via e2e.

    The default test bench settings are just meant as an information.
    You can change VIN, VOUT and Iout according to your needs.

    The following features are not modeled, so they cannot be used in the simulation:
    - clock synchronization, - Clock dithering, - Switching frequency program by RT.
    Enter the desired switching frequency (FSW) in the script window (F11).
    So, it is for example not possible to feed an external clock signal into the SYNC pin, nor to enable ditheriing.
    The switching frequency can be configured, but this value has to be entered via the script window, instead of using a resistor on the RT pin.

    Best regards
    Harry

  • 0
    Prodigy 50 points

    heiio harry-san,

    Hello Harry

    Thank you for answering.

    I'm sorry, but could you please tell me more about the simulation model?

    I changed the HO/LO connection for this simulation model, but it seems
    that verification tends to fail.

    To verify the operation of this HO/LO, change to another manufacturer's MOSFET.
    I tried using Ti CSD18540Q5B, but the calculation often failed.
    At that time, the verification time was 3ms and the number of steps was 10ns.

    Is it effective to verify the LM5152-Q1 simulation model by adding component
    models from other companies?

    Best regards

    takahasi

  • 0 in reply to teruyoshi takahashi
    TI__Mastermind 19625 points

    Hello Takahashi-san,

    My first question is: Which simulation tool are you using?

    - Please do not use LT-Spice because this is not compatible to PSpice. So, our models will not work properly under LT-Spice.

    - When using a full-blown version of PSpice, everything should work fine, without limitations.

    - When you are using PSpice for TI, please be aware that there is a limitation to only three signal probes when you are using non-TI semiconductors.
    So, if the original model has worked for you, it may no longer work in the same way with non-TI FETs. You will need to reduce the number of measured signals to three.
    By the way, differential signals are already counting as two signals.

    Therefore, please start with the non-modified model first and make that one work.
    Then make small modifications step by step and verify which of these steps may cause issues:
    Modify voltages, voltage dividers, etc.
    Modify the switching frequency,
    Reduce the number of probes and modify a single FET first.
    Then modify the second FET.

    Best regards
    Harry

  • 0 in reply to Harry Hofner
    Prodigy 50 points

    heiio harry-san,

    The simulation model used is a pspice model.
    Compatible with psice model FET from the manufacturer.

    As shown in the attached document, I performed a simulation using the circuit at
    the bottom of the SIM sheet, but excessive overshoot occurred in HO.
    The cause is thought to be that there is a section where the level is temporarily
    low in HO/LO, and a through current is generated.
    Until now, simulation errors were caused by this overshoot that could not be
    handled by the calculation.

    Since there is no countermeasure against excessive overshoot,
    Any advice would be greatly appreciated.
    The FET in the attached document is
    Also, are there any recommended TI MOSFET products?

    Best regards

    takahasi

    DCDC(LM5152-Q1)SIMtest.xlsx

     

  • 0 in reply to teruyoshi takahashi
    TI__Guru 58641 points

    Hello Takahashi- san,

    as you have a very simple Model of a MOSFET on the high side which will have no turn on delay, I assume what you see here is a shoot through.

    This will be a due to that low side MOSFET switching of much lower then the model of the high side switch will turn on.

    Best regards,

     Stefan

  • 0
    Prodigy 50 points

    Hello Harry

    Thank you for answering.

    I have an additional question.
    The circuit diagram of the LM515-Q1 evaluation board (LM5152EVM-BST)
    When I checked, the FET was using a different product in HO/LO.

    Could you please tell me about the selection criteria for this FET?
    Currently, when I connect the same FET to HO/LO, there is a
    time when both go to L level when HO rises.

    I would like to solve this problem, so please tell me the reason for
    selecting the parts for the evaluation board.

    Best regards

    takahasi

  • 0 in reply to teruyoshi takahashi
    TI__Mastermind 19625 points

    Hello Takahashi-san,

    You wrote:
    > ... there is a time when both go to L level when HO rises. I would like to solve this problem ...

    The fact that BOTH FETs ARE OFF for a while before one of them turns ON is not a problem.
    Instead, this so-called dead-time is a MUST to avoid a cross conduction across both FETs.

    Or do I misunderstand you and the effect that you8 describe is some kind of dip AFTER the dead-time?
    In that case, please introduce small gate resistors (maximum 5 Ohms) to slow down / flatten the turn-on times (also see my remark below).


    On the EVM, the 8.8 Milliohm of the NVMFS5C670NLWFAFT1G would be too much for the high side FET, therefore the NVMFS5C645NLWFAFT1G was chosen.
    For the low side FET, I guess, the designers just kept the cheaper FET. I do not see any reason why the NVMFS5C645NLWFAFT1G should not work on the low side as well.

    In fact, the alternative part (BSC022N04LS6) would be the same for high side and low side.


    Here is one important remark:

    The gate drivers of the LM5152 are very strong and designed for a dual FET constellation.
    When single FETs are used, please insert gate resistors for both FETs.
    The value of the gate resistors actually depends on the chosen FETs.
    For single FETs I would recommend that you start with a value of about 3 Ohms. Do not go above 5 Ohms.
    For identical high side and low side FETs, please always keep both gate resistors the same, otherwise the adaptive dead-time mechanism cannot work properly.

    Best regards
    Harry

  • 0
    Prodigy 50 points

    Hello Harry

    Thank you for answering.

    I followed your advice and tried adding a resistor to the base side of the FET.
    It was not possible to improve the timing at which both the HO falling and LO
    rising timings go from about 5 ns to 8 ns to H level.

    When I checked the current waveform, I found that no through current occurred
    and the output voltage and current were stable at the desired output voltage and current.

    Doesn't a through current occur during the dead time on the LO side?

    Best regards

    takahasi

    DCDC(LM5152-Q1)SIMtest_2.xlsx

  • 0 in reply to teruyoshi takahashi
    TI__Mastermind 19625 points

    Hello Takahashi-san,

    Maybe I completely misunderstand your question.
    But, during the time when both FETs are OFF, why would you expect a current through the low side FET?

    A cross-conduction could only happen when both FETs are ON.

    Best regards
    Harry

  • 0
    Prodigy 50 points

    Hello Harry

    Let me capture yesterday's question.
    What I want to check now is that I intended to ask the question when
    the gates of both FETs turn on (H level).

    The part in the red frame in the attached image corresponds to this,
    and it appears that LO is turned on at a time when the HO voltage has
    not completely decreased.

    I checked the data sheet, but do you understand the recognition of tDHL,
    which controls LO to turn on by monitoring the timer from HO's OFF command,
    as shown in the attached image?

    In that case, is there any other way to prevent HO/OL on other than selecting
    a FET with small parasitic capacitance, which is related to FET mirror reduction?

    Best regards

    takahasi

  • 0 in reply to teruyoshi takahashi
    TI__Guru 58641 points

    Hello Takahashi-san,

    just to ensure an to align: on the high side you still have the PSpice primitives switch used?

    Assuming so:
    This will not have any capacitance like a real MOSFET would have - so adding just a resistor will not change any timings or the behavior.

    The internal dead time control is looking on the the voltage level of the Gate driver signals - so to model the behavior right and to get the right signals for the dead time logic a correct model of a MOSFET needs to be used with all the parasitic Capacitance (Coss/ Ciss/  Crss)

    Best regards,

     Stefan

  • 0
    Prodigy 50 points

    Hello Stefan-san,

    Thank you for answering.

    The waveforms I sent you the other day do not use PSpice primitive switches.
    The MOSFET will be a non-TI model.
    The parasitic capacitance (Coss/Ciss/Crss) of the FET is selected to be as small as possible.
    The capacitor was also changed to a capacitor other than the pspice model and measured.

    In addition to constant resistance, measurements were made using a constant current
    configuration as shown in the attached document.
    I removed the 10u+2mΩ ESR configuration on the output side that was included in
    TI's simulation model circuit in the constant current circuit.

    When I measured it, the output voltage waveform showed excessive noise as the
    FET turned on and off, and I think that the lib file for the added capacitor
    was not working properly.

    Even in this state, the waveform result still has dead time, so is there a way
    to check if it is correctly adapted to the additional model?

    Best regards,

    takahashi

  • 0 in reply to teruyoshi takahashi
    TI__Mastermind 19625 points

    Hello Takahashi-san, 

    There seems to be some mis-communication due to a different usage of the same term / phrase.

    You wrote: 
    > ... the waveform result still has dead time

    Can you please explain in detail in your own words what exactly you mean when you say "dead time" ?

    Thanks a lot

    Harry 

  • 0 in reply to Harry Hofner
    Prodigy 50 points

    Hello Harry-san,

    I think this dead time is the time during which LO rises before HO falls to L level.

    The measured dead time is about 10ns.

    Best regards,

    takahashi

     

  • 0 in reply to teruyoshi takahashi
    TI__Mastermind 19625 points

    Hello Takahashi-san,

    You wrote:
    I think this dead time is the time during which LO rises before HO falls to L level.

    Thanks for the confirmation. This explains the mismatch in the communication.

    In the literature and in our understanding, the dead-time is the time while both FETs are OFF.
    So, this is a must-have and not something to avoid.


    What you describe is some kind of overlap, when one FET is still on at the time when the other FET also turns on already.

    Our device is using an adaptive dead-time control which will avoid such a constellation.

    Then you look at the voltage between the HO pin and GND, this is NOT the signal when the high-side gate driver is ON.
    Instead, it is a mix of the switch node voltage plus the high-side gate driver voltage on top.

    To get the real driver output signal, you will need to subtract the switch node voltage from the voltage on the HO pin.

    When you look at the purple signal you will basically see three levels: 0V, 13.5V and 18V.
    During 0V and 13.5V phases, the high-side gate driver is OFF.
    When it turns on, it will add around 4.5V on top of the 13.5V of the switch node which results in the 18V that you see.
    The high-side driver is only on while the HO signal is at the 18V level.

    When the LO voltage goes down from 18V to 13.5V, the channel of the high-side FET turns off.
    BOTH FETs are turned off from that point on.
    But the current can still flow across the body diode of the high-side FET and the switch node voltage remains at 13.5V.

    At the point when the low-side FET turns on, it will actively pull the switch node to GND.
    At this time, you will see the big step in the HO voltage from 13.5V down to 0V.

    But the high side FET has already been turned off about 25ns earlier (when the HO voltage had dropped from 18V to 13.5V).

    A similar thing happens at the other transition.
    When the LO turns off, you can see the switch node going from 0V to 13,5V and the HO voltage goes with it.
    But this is NOT because the high-side driver has turned on.
    The input voltage (through the inductor) basically defines the voltage of the switch node at that time.

    About 20 .. 25ns afterwards, you can see that the high-side driver turns on. This is when the step from 13.5V to 18V happens on the HO pin.

    So, the dead-time is about 20ns, as expected. There is no time when both FETs are on simultaneously and there is no overlap nor shoot-through.

    Best regards
    Harry

  • 0
    Prodigy 50 points

    Hello Harry

    Thank you for answering.

    I realized that I had a misunderstanding about the operation of FET.

    I have another question, so please let me ask.

    I was investigating the transient response using a constant current load (CCCS) configuration.

    There was a difference in the output voltage waveform depending on whether C135 and R11 (2mΩ and 10uF) of the CR circuit were installed or not.

    Is this CR circuit essential in this kind of circuit configuration?

    Note that C118 and C114 are electrolytic aluminum capacitors.

    Best regards

    takahasi

  • 0 in reply to teruyoshi takahashi
    TI__Mastermind 19625 points

    Hello Takahashi-san,

    For a switch mode boost converter, you should generally use multiple 4.7µF and/or 10µF CERAMIC capacitors on the output side (not just electrolytic capacitors).

    The size of external components like the output capacitors, an external feedback divider (which does not exist in case of this device), etc. will all have an influence on the transient response.
    The compensation network will need to get re-calculated accordingly.

    To create a Bode plot, you can also use the QuickStart calculator which you will find here:
    www.ti.com/.../SLVRBL5

    Please keep in mind that the transient response on a real board will be influenced by parasitics of the PCB.
    Therefore, the simulations will only give you a starting point, and the real compensation will need to be de determined by experiments in the lab.

    All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults” and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml).

    Best regards
    Harry