TPS563201: TPS563201 EN pin biasing

Hi Robin,

the 9V on EN pin won't cause a problem. 

If EN is connected to GND, The IC can be disabled.

Best Regards,

Shipeng

Thanks, good to hear.  We need to ensure the chip is disable when USB power is connected, and the datasheet didn't show the body diode that effectively powers the chip from any power source on the output!!

It seems that the 56320X DC-DC converters are not ideal for audio or radio use as they generate a lot of EMI, especially in Eco-mode.
I suppose there is no way to really significantly reduce the EMI?  We have a 4 layer board, have buried the FB line between ground layers, kept every trace as short as possible and followed the PCB layout guide, we are on out 4th revision board and put the LCD backlight load TPS61165 onto the 563201 to try to stop it running Eco-mode, which helps a little.  In contrast, the 61165 produces no detectable EMI.

Forgot to say, so connecting EN to ground via a 10K resistor will be sufficient to shut it down?

Hi Robin,

It will be better if you use TPS563208 which works in FCCM mode.

The enable or disable of the IC is decided by the voltage on EN pin instead of the resistor in fact. 

Thanks.

Shipeng

Thanks, I'm reading the TPS563208 datasheet now, so is Pulse-skip mode the same as Eco-mode, which was generating more EMI?

Is continuous current mode with Eco-mode disabled?

I just searched on Digikey and found the TPS563208DDCR, is that a drop-in replacement for the TPS563201DDCR?

I was being supported by Harry Zhou who recommended the 563202, but he hasn't replied to my emails in a month.

Hello Shipeng, thank you for the information!

So the 208 sounds like the answer to our problem which would be fantastic!

I presume that the 208 disables both Pulse-skip and Eco modes in order to reduce EMI?

Best regards

Robin

Okay, we've ordered the 208 part to test, thanks for letting me know.  I will post the results.

Hi, revising the 208 datasheet, I see there are now 2 x 10uF input capacitors, so we have C12+C13, C11 is the 0.1uF.  We also had 3 x 22uF caps (C6-8) on the output, the datasheet shows 2 now, but I've left it with 3x22uF, is that okay?

Here is our layout, please could you take a look and let me know if anything can be improved?

Hi Robin,

M colleague Shipeng will give you response soon. Thanks!

BRs

Lucia

Hi Robin,

It's no problem that you put 66uF at output. 

For layout, the GND connection is not very good. Do you have a GND plane on inner layer?

Thanks.

Regards,

Shipeng

Hi Shipeng, the datasheet says not to allow ground currents under the chip and shows the same in the PCB example, but there is gnd plane on the earth layer directly below the top layer, and on the back layer the same.

The black areas shown are free of tracks and planes as per the datasheet.

Hi, any chance of confirmation please, that the areas without ground plane shown in black are correct?  It's a 4 layer board, all layers in the last image's green area are ground plane, and there is a ground plane link track in blue, back layer across the centre gap under the orange SW track.

Hi Robin.

You may misunderstand our layout guideline. You can see our EVM board layout as a reference.

https://www.ti.com/lit/pdf/slvuak7

Thanks.

I can't see the difference.  In the eval board layout there is no ground under the IC or inductor, like mine, the rest has ground plane, like mine.

Can you specify where the problem lies with our layout?

In the eval PCB there is ground on the entire bottom layer under the IC and inductor.
The SW trace is on the bottom layer, with ground plane on the top layer above it, which is not done on the datasheet PCB example, i.e. no ground plane in the SW trace area.
In the datasheet PCB example a ground plane below the IC was also not used.
Is there anything else I should consider?

The problem from my POV with the layout guidance is that many people will have 4 layer boards, and there is no advice on the inner layers.
Should inner layers be ground plane, or deleted?  Under the could no layers at all, that is clearly shown.

Correction, there is ground below the coil on the bottom layer.  Would be good to be able to edit comments!

There seems to be a better reference for PCB layout in the Application Report titled "Optimize DC-DC Layout for SOT Package to Improve Thermal and Voltage Spike"

Hi Robin,

There's only a 2-layer example so in 4-layer application, you can think it as the top layer and 1st inner layer, and the other 2 layers are free of use. 

In our EVM board, there's no ground under the inductor but there's ground under the IC.