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UCC21750: Inquiry about MOSFET parallel drive.

Part Number: UCC21750

Hi

How many MOSFETs can be run in parallel on the ucc21750?
I don't have a problem with up to 2 at the moment, but I want to know how many will be possible.

It is a 50KW system and will consist of PFC and LLC.

Thanks

  • Hi David,

    How much voltage is across the FET, and how much current will be flowing through it when it switches? What is the switching frequency? With this information, you can select a FET that will stay below a safe temperature with the available heat-sinking. 

    Finally, you should select a gate driver that has enough output current for a fast switching speed, but also can provide helpful protection features for larger switches. The UCC21750 is designed to drive modules, which have built-in optimized layout, and it can monitor the module temperature, monitor overcurrent conditions, and clamp Miller charge injection.

    You can drive many small, high Rdson FETs in parallel, or one large, low Rdson FET and get the same switching loss. The thermal resistance of multiple FETS would be lower, but the inductance for the Miller charge injection would be unacceptably higher.

    Suffice to say, the best overall design is usually ONE appropriately sized FET or Module the avoids adding inductance and creating Miller injection hazards, while also making sure the switch is large enough or efficient enough to avoid overheating. You can put more in parallel to save cost if you overdesign for peak current, but such a design will not be able to switch as fast or quietly for high-end applications.

    Best regards,

    Sean

  • Hi

    The Qg of the sic MOSFET to be used is 288 nC.
    If two are used in parallel, the IVDD is as follows.

     IVDD = (Qg1+Qg2)*Fsw.

               = (288nC+288nC)*100kh

               = 57.6mA

    Did I calculate it correctly?
    Is this value available if it is less than Is compared to Is in data sheet?

    Thanks

  • Hi David, 

    Why did you select this FET? Will 2 of these FETs efficiently conduct the all current that you need?

    Your IVDD equation indicates how much DC current your power supply will need to deliver to the gate driver. That I_s safety limiting value indicates how much current in a worst case failure would provide enough energy to possibly crack the die and compromise the isolation barrier. Some customers design for a DC current below this value, and then sequester DC supply current to 61mA or less using an LDO. Since your 57.6mA is below the 61mA, you could add this type of protection if you wish.

    Driving two FETs in parallel "well" is a subjective assessment. Your switching losses will always go down, but maybe not by the full1/2 if the gate driver is not large enough. The best way is to test, but my rule of thumb is that you need about 1A of output current per 1nF or Ciss. UCC21750 is a 10A driver, and can probably drive 10nF of Ciss without losing any efficiency.

    If you use an external Rg, then the efficiency will go down also.

    Best regards,

    Sean

    Various gate drivers driving 3 Parallel NTH4L015N065SC1:

    60A, 600V, 18Vgs

    1 single NTH, 30A, 450V, 18Vgs: