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UCC28711: UCC28711

seungpyo kang
Prodigy 210 points
Part Number: UCC28711

It is understood that the switching frequency of UCC28711 varies with output. (I have seen that UC28C40 is used by connecting resistors and capacitors for user settings).

Looking at the datasheet of UCC28711, there are frequency modulation mode and magnitude modulation mode, and it seems that it is automatically selected in certain ranges.

Am I correct in understanding that the product does not need to have the switching frequency fixed arbitrarily?

  • 0
    TI__Mastermind 24375 points

    Hi Seungpyo,

    Thank you for reaching out.

    Yes you are correct. The max switching frequency for a design will be limited by the value of Lm and Ipk.

    The controller can switch upto 100khz (specified in datasheet), care must be taken Lm and Rcs are chosen to not violate beyond this limit.

    Regards,

    Harish

  • 0 in reply to Harish Ramakrishnan5
    Prodigy 210 points

    I believe that the voltage from the HT+ point to the grounding point of the HV Start point is determined solely by the input voltage, regardless of the on/off state of the MOSFET. And after moster Q2 ON, VDD will charge.

    However, in my case, the voltage level of D13 fluctuates as follows. Additionally, while the gate voltage of DRV outputs three as specified in the manual, it does not output thereafter. (The load side is under no load condition.)

    CH1:VDD (C10 Voltage)
    CH2: Zener Voltage (D13-PGND)

    CH3:Q2 Vgs

    What I'm curious about is:

    1. Is there anything wrong with my generator voltage?
    2. Is there a problem with the operation of the gate voltage?
  • 0 in reply to seungpyo kang
    TI__Mastermind 24375 points

    Hi Seungpyo,

    The above is a typical startup waveform.  Vdd charges to ON threshold, at which instant it gives 3 pulses on DRV to get the output voltage and aux voltage up. If there is a fault during this time the IC shuts down and this is normal behavior.

    The hv pin waveforms look ok. There is an internal logic which enables current source to charge Vdd when capacitor is charged (clamped to certain voltage) and when it reaches UVLO off limit it probably sees the input voltage.

    Regards,

    Harish

  • 0 in reply to Harish Ramakrishnan5
    Prodigy 210 points

    I'm sorry, I keep having a lot of questions. And Thank you !

    I understand your response as follows:

    Input voltage is applied to the HV pin -> Internal UCC28711, IHV current source operates (that is why CH2 voltage is decrease in my upper qeustion) -> C10 capacitor on the schematic is charged -> UVLO threshold value is exceeded -> 3 pulses are generated from DRV -> If all things are okay, operation continues, but in case of a fault, operation stops.

    It is my understanding, and it is correct, that there's a fault in my SMPS.

    My question is:

    1. I believe that if no abnormal voltage is applied to the VSpin, VFB, and CS pins at the moment, it can be assumed that there is no fault. Is that correct?

    2. If  secondary side, no load condition, it doesn't seem like there's a corresponding situation labeled as a fault in the datasheet. Is this also correct? Is it possible to consider the absence of load as unrelated to the current fault occurrence?

  • 0 in reply to seungpyo kang
    TI__Mastermind 24375 points

    Hi,

    1. If there is no abnormal voltage on Vs it will not trigger OVP, CS abnormal voltage triggers OCP. So this has to be verified with the threshold for OVP and OCP specified in the datasheet - 4.6V for Vs and 1.2 for CS. Also if sufficient input voltage is not present above the brown in voltage defined by Ivsl(run) threshold and Rs1 and turns ratio (Npa), this can also create startup issue.

    2. Yes fault can be triggered in no load also. Even in no load OCP or OVP is possible.

    Thank you

    Regards,

    Harish