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TLV840: RESET delay using Manual Reset input

Clement Lochu
Prodigy 30 points
Part Number: TLV840

Dear Support,

I am using the TLV840MADL29DBV in a design to add a delay to a reset signal generated by an FPGA.

The FPGA drives the /MR input with a 2us low pulse to start asserting the /RESET low (so 2us > tMR_PW).

I left the CT pin open so the delay should be 40us typ / 80us max as described on the datasheet p7.

As I understand it, after /MR is logic high again, the delay circuit should keep /RESET low for the 40~80us.

I tested the function, but the /RESET output is only drive low for 2us and release high...

Please find attached the schematic and the scope capture.

Did I missed something? Could you please clarify this point?

Thank you very much for your help.

Kind regards.

  • 0
    TI__Genius 9660 points

    Hello,

    I am looking into this issue and will get back to you tomorrow.

    Thanks,

    Walter

  • +1
    TI__Genius 9660 points

    Hello, 

    In order to enable the reset delay for the manual reset, there needs to be some capacitance on the CT pin. I measured a 40us delay using a 56pF capacitor and a 70us delay using a 200pF capacitor. This is the longest delay I could create with a 2us /MR pulse. Using a larger capacitor with the same 2us /MR pulse will remove the delay. A larger /MR pulse is needed for a larger delay.

    Thanks,

    Walter

  • 0 in reply to Walter Zollinger
    Prodigy 30 points

    Hello Walter, thanks for your help.

    I tried to add a 68pF capacitor and keep the 2us low pulse on /MR, and I got 42us delay on the /RESET signal, so it works.

    To my mind, the datasheet is not very clear on this point because on section "7.8 Timing Requirement", I read that the typical delay is 40us when CT is open, however we need to add a small cap to get this delay.

    Anyway, thanks for your support :)

    Best regards.