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Similar question came up on internal forums, I gues these are related/same -
256FSCLK is a clock for McBSP_CLKS (on OMAP) so that OMAP and TPS clocks are synced. It has nothing to do with the I2S interface clock.
I don’t know the usage for this customer. Generally this device is used as power companion with OMAP and McBSP interface is connected to I2S on TPS.
Hope this helps.
We are seeing this same behavior. In our application we receive an external word clock and use pll's to generate oversampling clocks for the various other adc/dac's on board. The documentation for the TPS65930 seems to imply that while it can't use an oversampled clock as input, it can generate one via some internal PLL from a word clock input. However the 256FSCLK seems totally unrelated to the input wordclock and is instead locked to HFCLK or something. Is there someway to actually turn on this PLL?
Am I the only one who cannot see any text in the body of Gary Morrison's question/posts?
I cant see Gary's comments either.
The 256FSCLK is the only option on this pin. The source for this clock is HFCLK on the device. You cannot generate any other clock on this pin.
I'm not actually using 256FSCLK for anything. It is just connected to a test point. Looking at the datasheet again I see that the oversampling clock is always generated from HFCLK. Is there another way to achieve having the i2s port in slave mode with an i2s_sync asyncrhonous to HFCLK? Perhaps by using the BT_IF instead of VOICE_IF?
This really depends on your architecture. If HFCLK oscilaltor feeds to the PMIC and PMIC provides the clock to the processor then you have a synced system with only one clock source.
Using BT or VOICE i/f doesnt help in having a sync. Also, all systems I know so far have used PMIC I2S interface in master mode, so if you are using in slave you will have to ensure that the clocks are synced else you will certainly see data packets being lost.