TPS65987D: TPS65987D　 I connected a high-speed SSD memory, but the data transfer speed was slow.

Hi Yamamotoju,

Due to the holiday, many device experts are currently out of the office. When they return they will look into this and provide a response. Please expect some delay accordingly.

Thanks,
Field

20230912_ui29_1210.pjt

Mr. Alex
We will send you the project file.
The GPIO assignment of our development board is
GPIO0 →"Port 0 USB3 Event"
GPIO2 →"Port 0 DP Mode Selection Event"
GPIO3 →"Pin Multiplexed to Altemate Function(DP HPD Port 0)"
GPIO21 →"Por0 Cable Orientation Events"
Can you think of any other hardware-related factors?

Yamamoto

Hi Yamamoto,

Do you have access to I2C1 from the PD on your board? If you do, you can try and read register 0x5F Data Status register for details on the connection made with the SSD. 

Below are my comments on the GPIO setup:

GPIO0 - Port 0 USB3 Event should trigger on connection of the SSD but it is not in your case. This means the PD may not be recognizing the connection as a USB3 connection. 

GPIO1 - Port 0 DP Mode Select Event should not trigger on connection of the SSD because the SSD does not support DisplayPort.

GPIO3 - This is again tied with DisplayPort, which the SSD does not support. This will remain low.

GPIO21 - Port 0 Cable Orientation will flip with the connection orientation.

Next step I recommend taking is to gain PD_I2C1 access from your board, so you can read some status registers. Without this information, we are unable to tell what connection is made with the SSD or what is the root cause of the low data rate.

Best,

Alex 

Mr. Alex

thank you for your reply.
Reports the result of 0xF5 register.

Not connected → 0000000000
Type-cHub1 → 3305000000
Type-cHub2 → 3105000000
SSD direct connection 1 → 0300000000
SSD direct connection 2 → 0100000000

*1 is front side 2 is back side

・Do I need a software driver?
・Is it a hardware problem?

Yamamoto

Hi Yamamoto,

From our register definition for register 0x5F, the PD does not detect any USB2 or USB3 connection at all when the SSD is attached. In order for the PD to detect the connection type and report the correct connection, the SSD must respond to the PD's Discover Identity request message. Could you please read out register 0x48 so we can see if the SSD responded?

If you have access to a PD analyzer tool such as TotalPhase or EZ-PD, you could use that to capture the PD messaging for more information. There should not be a hardware issue since the type-C hub you used was working with the PD. There is no software driver for the USB-PD connections, if needed after we find the root cause, we can change the PD configuration.

Best,

Alex

thank you for your reply.
Although the confirmation is delayed, I will inform you of the result of the 0x48 register.
SSD direct connection (byte length 28) All “00”
→'00000000000000000000000000000000000000000000000000000000
Type-c Hub (byte length 28)
→ 44E804006C00000000120220A0390000000000000000000000000000
Were there any factors that could lead to this phenomenon in the project file you sent earlier?
Is there any problem with setting the other "ADCIN1" terminal to (DIV=0.9) "BP_NoWait"?

Hi Yamamoto,

BP_NoWait is the fastest boot mode from a dead battery scenario. Dead battery is when PD boots from the type-C port without system power. In a normal scenario when PD/system is already powered at connection of the type-C device, dead battery mode does not apply.

From the result of the register 0x48 read, it looks like the PD did not send Discover Identity message to the far-end connected SSD. Combined with the result of the register 0x5F read you did before, it looks like the SSD is type-C only, so we would not do the same discover identity sequence that we do for PD. That being said, there should still be a USB3 type-C connection.

Do you have a way of capturing the CC signals using a scope or analyzer? Please try to capture the CC signals and also read out the 0x69 Type-C State register. This will help us see the CC voltage levels and see if a connection was made properly. Additionally, if you want to send me the schematic for your board, I can take a look and check the connections as well.

Best,

Alex

Mr. Alex
thank you for your reply.
We are currently preparing to submit the circuit diagram, but we need to confirm it first.
I may be misunderstanding
Table 3-12. 0x28 Port Configuration Register Bit Field Definitions (continued) Bytes 1-2: Port Configuration
 14:13 USB3rate(2) {(2) Initialized by Application Customization.}
 It seems that you can set USB3 with , but is it possible to adjust the speed by writing arbitrary settings to this register?
 00b USB3 not supported
 01b USB3 Gen1 signaling rate supported
 10b USB3 Gen2 signaling rate supported
 11b Reserve
Yamamoto

Hi Yamamoto,

The USB3.0/3.1 rate field of 0x28 Port Configuration register is used to set the maximum USB3 data rate for PD connections. If you select USB3 Gen2 for example, that will be the maximum speed of a USB3 connection on the port, but does not necessarily set the actual USB3 connection speed. The PD will determine the USB3 connection speed to report based on a combination of the USB3 rate field and the cable VDO response (PD message). So technically it is possible as long as the max USB3 speed set by the PD is not higher than the max USB3 speed supported by the SSD or other device.

• If USB3 Rate in 0x28 Port Config = USB3 Gen2 and max USB3 speed supported by SSD = USB3 Gen1
  • USB3 speed of connection = USB3 Gen1
• If USB3 Rate in 0x28 Port Config = USB3 Gen2 and max USB3 speed supported by SSD = USB3 Gen2
  • USB3 speed of connection = USB3 Gen2
• If USB3 Rate in 0x28 Port Config = USB3 Gen1 and max USB3 speed supported by SSD = USB3 Gen2
  • USB3 speed of connection = USB3 Gen2

In our debug, the USB3 SSD you tested with did not negotiate a PD connection with the TPS65987D, so the connection is limited to low non-USB3 speed. The issue is with establishing the PD connection with the SSD. Once this occurs properly at connection, USB3 speed should be established normally.

It is difficult to debug this without a PD analyzer. I recommend obtaining one, it will also help debug in the future, if it is needed. The next step I recommend is to read out register 0x69 when the connection with the SSD is made, for information on the CC pins and type-C state.

Best,

Alex

Mr. Alex
thank you for your reply.
I would like to confirm the contents of your comment.
Also, regarding "if you want to send me the schematic for your board, I can take a look and check the connections as well.", we will send you a document with an excerpt of the circuit diagram, so please check it.
The materials we will send
(1) Circuit diagram around TPS65987D
(2) Circuit diagram around TUSB1046AI
Our system intentionally does not allow PD (Power Delivery) to function.
Also, power is already being supplied to our system when a Type-C device is connected, so what is the appropriate setting for the "ADCIN1" terminal?

Hi Yamamoto,

The schematics look ok. I do not suspect this is a hardware issue.

I did check again on your project and there is just one setting that could be impacting the USB2/USB3 detection at the port. I toggled the USBCapable field of the 0x32 TX Source capabilities register PDO1 to true. Please test this configuration and see if anything changes.

20240421_ui29_1210.pjt

Since your system does not boot from the type-C port in dead battery condition, you do not need to worry about the ADCIN dead battery configurations. The ADCIN2 pins will only be used to set the I2C address like below. The ADCIN1 pin is a "don't care" from the PD point of view unless booting with no system power.

Best,

Alex