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TPS55340: Condition for Sync pin

Shota Mago
Expert 7150 points
Part Number: TPS55340

Hi team,

Is there any condition for applying external clock on SYNC pin?

For example, when external clock source is stopped, then resume applying clock, is there any concern?

It seems that datasheet doesn't mention any details for timing requirement of SYNC pin. 

Best regards,

Shota Mago

  • 0
    TI__Genius 16925 points

    Hello Shota, 

    Thanks for reaching out to us via e2e. 

    Currently most of our team is out on vacation. 

    I will come back to you before the end of the week.

    In the meantime, can you please explain in more detail, what exactly you would like to do?

    Do you want to use interrupt the sync signal to stop and re-enable the converter?

    Or are you thinking about the start-up or shut-down procedure?



    Best regards

    Harry.

  • 0 in reply to Harry Hofner
    TI__Expert 7150 points

    Hi Harry,

    Thanks for your reply. Noted that most of your team is out on vacation currently.

    Answering by beginning of next week is helpful.

    Harry Hofner said:
    can you please explain in more detail, what exactly you would like to do?

    My customer has been using TPS55340PWR with external clock sync for their products.

    Recently, they noticed that when reset is applied for clock source, clock for the SYNC is stopped temporally and resume.

    So there is a short period of time that external clock is not applied on SYNC pin. 

    At the period, the SYNC pin is not shorted to GND whereas the datasheet states it should be tied to AGND.

    That's why they would like to make sure if there is any requirement for the SYNC pin.

    Best regards,

    Shota Mago

  • +1 in reply to Shota Mago
    TI__Genius 16925 points

    Hello Shota,

    Thanks for the reply.
    Looks like I need to ask my question in a different way:

    When will the gap in the external clock signal happen?
    - While the converter is boosting?
    - Or while the converter is disabled (via EN pin or while the input voltage is too low)?

    Without the external sync signal the oscillator should fall back to the frequency which is set by the resistor on the FREQ pin.
    This is why the external clock frequency must be within ±20% of the corresponding frequency set by the resistor.

    But anyway, I would believe that this transition is not really smooth, so it can cause unexpected conditions in your output signal.

    In the documentation for our EVM and PMLK boards there is no hint that this pin HAS TO BE connected to GND when not used.
    So, I am confident that the recommendation to connect the SYNC pin to GND is mainly to avoid that any noise gets picked up by a floating pin.

    All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults” and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml).

    Best regards
    Harry.

  • 0 in reply to Harry Hofner
    TI__Expert 7150 points

    Hi Harry,

    Harry Hofner said:
    When will the gap in the external clock signal happen?
    - While the converter is boosting?
    - Or while the converter is disabled (via EN pin or while the input voltage is too low)?

    While the converter is boosting.

    Harry Hofner said:

    Without the external sync signal the oscillator should fall back to the frequency which is set by the resistor on the FREQ pin.
    This is why the external clock frequency must be within ±20% of the corresponding frequency set by the resistor.

    But anyway, I would believe that this transition is not really smooth, so it can cause unexpected conditions in your output signal.

    Thanks for your answer. Let me double check.

    When the external clock is stopped, the device is operated by internal oscillator which is set by FREQ pin. When external clock is recovered, the device is sync with the external clock again. But these transition are not smooth and output might get some fluctuation.

    Is this understanding correct?

    Best regards,

    Shota Mago

  • 0 in reply to Shota Mago
    TI__Genius 16925 points

    Hello Shota,

    Yes, your understanding correct.
    The PLL will somehow try to synchronize again to the external clock.

    We cannot predict the effect that it has on the output. Slight changes in the timing / phase shift between internal and external signal may result in different effects.

    All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults” and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml).

    Best regards
    Harry.