• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 62 subscribers
  • Views 182 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS65219: GPO2 Power Off / Reset State

Nic Bergmann
Prodigy 90 points
Part Number: TPS65219
Other Parts Discussed in Thread: TLV62585, TPS22965

For TPS65219 configurations that have GPO2 enabled (typically used to sequence an external 3.3 V load switch / supply), what is the state of that pin when the PMIC is in the 'OFF' or unpowered (VSYS = 0 V) state? Is it still held low? Since that signal is an open-collector output that requires a pullup (to VSYS as recommended by the documentation), I am concerned about it rising along with VSYS until the PMIC has turned on enough to control it (i.e., glitching) and therefore creating a race condition between the PMIC's undervoltage lockout (UVLO) and that of the power switch's / supply's and its associated enable ('EN') input.

Thanks!

  • 0
    TI__Mastermind 19555 points

    Hi,

    Thank You for using E2E! The GPO2 on pre-configured TPS65219 devices ramps with the pull-up supply until the voltage on VSYS goes above the POR threshold. If this would trigger an ON-request for the IC that is being driven, we would recommend adding a pull-down that can define the initial state.    

    Let us know if there are any additional questions. 

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    Prodigy 90 points

    Thanks for the reply, Brenda!

    Do you have a recommendation on a pull-down resistor value and, correspondingly, the pull-up resistor value? Since the GPO2 pin is an open-collector output, this configuration, essentially a voltage divider, gets a bit tricky. My VSYS is 5 V, I'm using the 02-version of the PMIC, and my external 3.3 V supply is TLV62585.

    I believe the rising UVLO for the buck is 2.45 V and the PMIC is 2.305 V. So, on paper, the PMIC should take control, not accounting for the delay from UVLO to GPO2 control, prior to the buck turning on. But, the approximately 100 mV margin doesn't give me a lot of confidence.

    Interestingly, I believe this "issue" exists on the latest eval board, SK-AM62B-P1, with the 04 PMIC and TPS22965 power switch. It might actually be "worse" as that power switch turns on much earlier than my buck. Perhaps this is not a really an issue as the DVDD3V3 domain is the first in the AM62x's power sequence anyway? Though that doesn't really align with the recommendation to use GPO2 for sequencing then.

    ~Nic

  • 0 in reply to Nic Bergmann
    TI__Mastermind 19555 points

    Hi Nic,

    You could implement a logic with PMOS to disconnect a 100K Ohms pull-down when GPO2 is released. Another option is to evaluate your prototype with a 10K / 10K resistor divider. This resistor divider would put 1.2V on the enable pin of the external 3.3V discrete when the voltage on VSYS is approximately 2.4V.  

    Thanks,

    Brenda