Hi team,
My customer has TPSM82903SISR designed into their board powering an ASIC analog rail (12Vin to 0.82Vout @ 2.5Amax, 1MHz switching). That ASIC has a pretty stringent tolerance requirement, where it recommends no more than +/-1% noise on the rail. The customer is nervous to pull the trigger on the board design and find out that either the Vp-p is not good enough, or load transients need to be tighter, or both. I am investigating the possibility of adding an LDO on the output stage, but I wanted to understand the following from you:
- First idea is of course to increase Cout to reduce output ripple. I'll recommend this, but not sure how much that will affect transient response. Don't want to help one problem and create another.
- This is an internally compensated part, but I am thinking about asking the customer to place a spot for a feed forward capacitor so they have a knob to turn in case transients become a problem. Any guidance on if that is a good idea and how to select the value of that Cff?
- If they can tolerate the efficiency hit, moving from 1MHz to 2.5MHz switching helps both output voltage ripple and transient response, right?
- Any other ideas? Webench recommended an input filter but it was too large so we abandoned that.
Thanks,
Brian
