TLV840: Is CT available to avoid the glitch when VDD<POR?

Tamio Yokokura

Expert 3960 points

Part Number: TLV840

Hi, TLV840 support team

TLV840CADL29 has a feature programming Reset Time Delay by an external capacitor.

I would like to know if it is available to avoid a glitch at following two case when VDD<POR.

When /RESET is pulled up to VDD
When /RESET is pulled up to other power supply , but it is applied before VCC is powered

Regards,

Tamio

over 1 year ago

0 Sila Atalar over 1 year ago

TI__Genius 9690 points

Hi Tamio,

Thanks for your question.

While the device is getting power, when VDD<VPOR, the output is undefined. After VDD is higher than VPOR, the device has enough power to be in the expected state, which is low since VDD< Vit. So you will most likely see the behavior that you highlighted red

Best,

Sila

0 Tamio Yokokura over 1 year ago in reply to Sila Atalar

TI__Expert 3960 points

Hi, Sila,

Thank you for your quick reply.

I will check the actual behavior using EVM.

Thanks

Tamio

Power management

Power management forum

TLV840: Is CT available to avoid the glitch when VDD<POR?