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TPS1663: The device doesn't assert FLT after SHDN=LOW because it is not a fault scenario

Conor
Guru 12155 points
Part Number: TPS1663

Hi,

The following E2E forums discuss FLT/SHDN. The forum answer states that "The device doesn't assert FLT when SHDN=LOW because it is not a fault scenario."

TPS1663: internal FET ON/OFF

[Question]

After the internal FET is turned off by the shutdown function, does UVLO work and FLT is asserted low?

Or when the device is turned off by the shutdown function, UVLO does not work and FLT is not asserted low?

 Looking at the internal block diagram, I couldn't find any circuit that relies on the shutdown function to determine whether FLT is asserted low.

 

Addendum

The customer wonders why FLT is not asserted low by ULVO after the internal FET is turned off by the shutdown function.

Best regards,

Conor

  • 0
    TI__Guru* 79181 points

    Hi Conor,

    FLT should go low if VIN goes below UVLO  but as per diagram what will happen is if SHDN is going low and VIN falls below POR threshold of 4.2V that will reset the FLT making it high again. In customer case SHND is going low and VIN is falling below 4.2V POR so that is causing some issue and preventing FLT to go low. 

    If you see in this highlighted region FLT is going back high again.

    Regards

    Kunal Goel

  • 0 in reply to Kunal Goel
    Guru 12155 points

    Hi Kunal,

    Kunal Goel said:
    In customer case SHND is going low and VIN is falling below 4.2V POR so that is causing some issue and preventing FLT to go low. 

    Thank you for your reply.

    I understand that the FLT of the device is asserted even in UVLO after the shutdown function.
    We are investigating the cause of "some issue and preventing FLT to go low" in detail.
    Information such as circuit diagrams has already been shared via email, but is it possible to receive additional comments?

    Thanks,

    Conor

  • 0 in reply to Conor
    TI__Guru* 79181 points

    Hi Conor,

    Both SHDN goin low and POR happening at same time will prevent FLT to go low as per logic.

    Regards

    Kunal Goel

  • 0 in reply to Kunal Goel
    Guru 12155 points

    Hi Kunal, 

    Based on your comments, are the following 1 and 2 correct?

    1.FLT is asserted low when the UVLO pin voltage falls below 1.12V. After that, if the P_IN pin voltage falls below 4.2V, FLT is pulled up (reset) to high.

    2. If the external shutdown function activates and turns off the internal FET before the UVLO pin voltage falls below 1.12V, FLT will not be asserted low even if the UVLO pin voltage falls below 1.12V. After that, if the P_IN pin voltage falls below 4.2V, FLT is pulled up (reset) to high.


    If the explanation in 1.2 is correct, we can explain the following behavior.

    Thanks,

    Conor

  • 0 in reply to Kunal Goel
    Guru 12155 points

    Hi Kunal, 

    Is it possible to receive an answer today?

  • 0 in reply to Conor
    TI__Guru* 79181 points

    Hi Conor,

    On the waveform can you mark point where VIN goes below UVLO and UVP(POR)?

    Regards

    Kunal Goel

  • 0 in reply to Kunal Goel
    Guru 12155 points

    Hi Kunal,

    Since R1 to R3 have the following resistance values, UVLO is assumed to occur at approximately 4.7V (4.57 to 4.83V). On the other hand, the datasheet states that POR occurs at approximately 4.2 V.

    I have sent detailed waveform information via email, so could you please check it? As a precaution, we will send you a waveform of the voltage value measured when a shutdown occurs.

    I have an additional question.
    Since MODE=GND on the system, the following content of the block diagram you showed does not seem to work.What do you think?

    Thanks,

    Conor

  • 0 in reply to Conor
    TI__Guru* 79181 points

    Hi Conor,

    I confirmed on bench that if SHDN is low then if VIN goes below UVP or POR it will not cause FLT to go low. Since in customer case SHDN is falling low it is preventing FLT to go low. That means below highlighted FET is off and FLT is will follow supply it is pulled up to. Looks like VDD5 supply is falling so FLT is slowly falling like VDD5 . We need to probe that also. Also we need to see what is making SHDN low. 

    If you leave eFuse device SHDN pin open it will go low when VIN goes below POR threshold otherwise it is pulled upto internal supply.

    Regards

    Kunal Goel