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UCC28950: SYNC pin function when used in slave mode

user6304160
Prodigy 140 points
Part Number: UCC28950


We are using UCC28950 in Slave mode.

Please tell me about the following.

Q1.What is the time from the falling edge of SYNC to the falling edge of CLK.

Q2.What is the falling threshold of SYNC to output CLK?

Q3.Please tell me what happens when SYNC falls when the CLK pulse is high.

The OUTA and B outputs are becoming like double pulses due to noise to the SYNC terminal, and I would like information on how to take countermeasures.

Best regards.

  • 0
    TI__Guru* 86216 points

    Hello,

    Your inquiry has been received and is under review.

    Regards,

  • 0 in reply to Mike O'
    TI__Guru* 86216 points

    Hello,

    The time you are talking about is TPW and this time is typically 2.5 us.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 140 points

    Hello,

    Check the waveform below.

    OUTB is inverted within 2.5us from the falling edge of SYNC.

    Isn't 2.5us the SYNC pulse width when used in master mode?

    CH1:SYNC,  CH3:OUTB

    Also, there is only one answer for three questions. Please answer the remaining two questions as well.
    Regards,

  • 0 in reply to user6304160
    TI__Guru* 86216 points

    Hello,

    You are measuring it incorrectly.  You should measure rising to edge to trailing edge of the sync pulse.

    From your plot it looks to be 2.5 us.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 140 points

    Hello,

    What period are you talking about? Please illustrate clearly.

    Isn't it correct to understand that the CLK signal is generated after the fall of the SYNC signal, and that OUTA and B are inverted according to the fall of the CLK signal?

    As I have said many times, please answer Q2 and Q3.

    Regards,

  • 0 in reply to user6304160
    TI__Guru* 86216 points

    Hello,

    After rereading this I thought the device was operating in the master configuration.  I was referring to the period of the sync signal (TPW) of being roughly 2.5 us from your waveforms.  My mistake.

    Please see the answers to your questions below.

    Q1.What is the time from the falling edge of SYNC to the falling edge of CLK.

    > This sync signal is supposed to provide a 90 degree phase shift when used correctly.

    > To do this the CLK actually will be a 45 degree pulse.

    > So the CLK period should be (45/180)*(1/fsw)

    Q2.What is the falling threshold of SYNC to output CLK?

    >I reviewed the data sheet and it is not given.  However, the SYNC comparator uses CMOS logic levels.

    Q3.Please tell me what happens when SYNC falls when the CLK pulse is high.

    >Please refer to figure 44 of the data sheet.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 140 points

    Hello,

    Thank you for answering.

    Regarding Q3, what I wanted to know is which of the following two patterns would happen.

    Best regards.

  • 0 in reply to user6304160
    TI__Guru* 86216 points

    Hello,

    It actually syncs the clock it is not ignored.  The time should be what is required based on the frequency and what is required to generate the phase shift.

    Regards,