Other Parts Discussed in Thread: PMP5123, PMP3162
Hi...
ucc2897a spec(p16) 8.3.1.14 VDD:one of the references
The capacitance on VREF and VDD should be in a minimum ratio of 1:10.
I want to ask if there is any reason for this?Thanks
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Hi,
The reason is to avoid VDD capacitors CDD voltage drop below its UVLO OFF due to transfer CDD stored energy before VDD UVLO ON to VDD UVLO ON as right at UVLO ON, the energy for the device comes nowhere except from CDD which energy will bias the IC and charge up VREF capacitors until an external bias can take over during which time CDD needs to keep its voltage above UVLO ON. This requires CDD value big enough so when consider engineering practice 10 to 1 is recommended,
Hi,
As long as VDD reaches its UVLO ON, the IC will turn on: If your green circuit can do then ok. But this circuit has nothing to do with the 10:1 question. Is your 10:1 question resolved?
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