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TPS2HCS10-Q1: recovery from SPI interface fault

Part Number: TPS2HCS10-Q1

Hi team,

Could you please advise how to recover from SPI communication fault where TPS2HCS10 cannot response to MCU?

Since there is no reset pin, do I need to pull both VBB and VDD below UVLO?

regards,

  • Tsuji-san,

    The device does have a SPI watchdog available that would put the device in limp home mode without a regular tick from the MCU. This would at least have it that if SPI communication is lost, the output states go into known modes.

    Normally, the SBC/PMIC would be responsible with managing loss-of-communication errors like this. Making VBB/VDD low would cause the device to go into sleep mode and be acceptable here.

    Best Regards,
    Tim 

  • Hi Tim-san,

    I am assuming MCU working correctly, but somehow TPS2HCS10 SPI block got stuck and cannot respond to MCU.

    I would like to recover from this state by MCU. 

    The device will transition to LIMP mode when VDD<UVLO. The device internal register and state machine will not reset at LIMP state, correct?

    In that case, only way to reset whole device is shut down VBB and VDD? 

    regards, 

  • Tsuji-san,

    Yes- this would be correct. The only way to reset the entire device without SPI communication would be to power cycle VDD/VBB. The SPI watchdog would be a good way to ensure the device is in a known state during failure, however.

    Best Regards,
    Tim 

  • Hi Tim-san,

    If the device fall into LIMP home mode by VDD_UVLO, are the internal registers held rest to initial state?

    Then you need to configure registers after you return to ACTIVE state by sending SPI command to leave LIMP?

    regards,

  • Tsuji-san,

    I just confirmed with our systems team that when the device goes into VDD UVLO that limp home is not entered. We will update the datasheet to accurately reflect this.

    To answer your question, however, when the device goes into limp home mode the register values are retained. 

    Best Regards,
    Tim

  • Hi Tim-san,

    1. Please send me correct state diagram.

    2. What is the exact condition that the device enter and leave from LIMP_HOME status?

    3. How does the device behave if VDD < VDD_UVLO only occurs?

    4. If VDD < UVLO occurs momently and then VDD returned normal operating range, the device automatically returned to ACTIVE state?

    5. If VDD kept < VDD_UVLO, register value are retained?

    regards,  

  • 1. Please send me correct state diagram.

    We will send over email.

    2. What is the exact condition that the device enter and leave from LIMP_HOME status?

    The device enters LIMP HOME state from ACTIVE (only state to transition from) if either LHI pin is pulled high or if SPI WD fault is triggered (if enabled). The LIMP HOME state only affects the channel output state. All diagnostics and protections are available.

    To leave the LIMP HOME state, the LHI pin has to be low and need an SPI command to write 1 to the LIMPHOME_STAT bit (W1C) in the CH_FLT_TYPE/FAULT_GLOBAL_TYPE register.

    3. How does the device behave if VDD < VDD_UVLO only occurs?

    We report the VDD undervoltage voltage condition in the bit2 of the CH_FLT_TYPE/FAULT_GLOBAL_TYPE register. But this may not be readable depending on the VDD voltage. The expectation is that the system (through an SBC/PMIC or voltage monitor) recognizes that the VDD voltage could be too low for SPI to work in the device - so would force LHI pin high to ensure that the outputs are in safe state and not dependent on MCU write. In the absence of voltage monitor, the SPI watchdog can also be used (if the fault tolerant time is acceptable).

    4. If VDD < UVLO occurs momently and then VDD returned normal operating range, the device automatically returned to ACTIVE state?

    The device never leaves the ACTIVE state if LHI is not pulled high (when VDD is below VDD_UVLO). 

    5. If VDD kept < VDD_UVLO, register value are retained?

    Yes, we have power input from the VBB pin to keep the registers alive.