BQ76200: Discharge MOSFET failure during Short circuit test due to delay in turn off

Hello Monica,

I see from the schematic that a lot of components are DNP, did you populate them during this test (D8/D7/R35)? All of these are recommended components to have for this device.

I would agree that the parasitic oscillations may be causing the FET failure. We have a good FAQ E2E post we refer to, when talking about FET failures:

• How to debug FET failure resulting from short-circuit testing

Could you get the gate-source voltage of the FET as well? You could use the MATH function of your oscilloscope to subtract the source voltage from the gate of the DSG FET.

Is the ferrite bead chosen targeting oscillation frequency? The beads should ideally have its highest impedance at the frequency of oscillation.

In the past we ran into oscillation issues as well, which were fixed after we added a small capacitor to the drain-gate of the DSG FET. Shown in Figure 6. DSG FET With Added Cgd of the FET Configurations for the bq76200 High-Side N-Channel FET Driver application note. This is highly system-dependent, so it may not work for you, but it may be worth trying out.

Best Regards,

Luis Hernandez Salomon

8360.High side driver.pdf

I have added New Schematic, Only 3 resistors are actually DNP, rest everything is connected

Hello Monica,

Thanks for the confirmation there. That's good.

I think if you can the measurement across R30 (essentially gate-source voltage) that may more clearly show what is going on during the turn-off. Regardless, I do think the oscillation is the main problem. Based on the waveforms you show, and looking at the drain voltage.

Have you performed any other tests? Such as increasing the DSG pin resistance?

Best Regards,

Luis Hernandez Salomon

Initially, we were performing test with Battery cycler. Then we connected pure resistive load. We observed that oscillations and delayed completely removed with resistive load. So that oscillation problem is resolved now. It was due to cycler load.

However, During continuous short circuit test (load directly shorted by contacted), Discharge Mosfet is damaging. We could see IC tried to pull down Gate voltage and Pack+ go to negative but then again Pack+ rises and Mosfet and fuse getting damaged.

Attaching Oscilloscope snaps(pink - DSG, DSG enable, yellow Pack+, green current). With MCU, Current is detected within 200 us. From Bq76200- Calculated dsg fall time is 5 us but it is taking some 100uS.

Hello Monica,

That would go back to the FAQ post I shared above:

• How to debug FET failure resulting from short-circuit testing

Now we can rule out the oscillations (Glad to hear that was figured out!).

Due to inductances on traces/loads or battery, there can be high voltage transients during the turn-off of the FET, if the spike is too large, it is possible to exceed the drain-source ratings of the MOSFET. 

It is also possible that discharge is too slow, and depending on the SOA of the FET and how long does it remain in its linear region, if it cannot handle the current during the turn-off, the MOSFET could break.

Finding the right balance on turn-on/off is what we probably need to figure out here. If turn-off is too slow, you can decrease the DSG resistor. 

Best Regards,

Luis Hernandez Salomon

As you rightly said, 

1. I tried to change Rdsg till 10 ohm. The graphs provided here are wrt Rdsg=10 ohm.

2. In order to operate Mosfet in SOA wrt shorct circuit, I need to increase number of MOSFETs in parallel in Discharge circuit?

3. Vds limit for selected MOSFET is 100V and we observed it is less than limit during testing. What is the way to limit oscillations during switching? I have connected capacitors and TVS diode at Pack+. I tried to add snubber circuit as well but no change in oscillations.

Request your suggestions?

Hello Monica,

If the FET is breaking due to it not being able to handle the current then yes, I think the only solutions would be to either:

1. Add more MOSFETs in parallel to increase their current capabilities
   1. Which actually, would also slow down the turn-off as well, so maybe it won't be too great, if the turn-off speed is what's causing problems.
2. Increase the turn-off speed further by using external circuitry. 
   1. There are many turn-off circuits that can be used. A typical local turn-off circuit we have used and see often used is a BJT local turn-off circuit. Which we show/describe in Section 5 Parallel FET Test Circuits of the Multiple FETs with the BQ76952, BQ76942 Battery Monitors application not, which although is for a different part, this concept still applies.
   2. Remember, if turn-off is too fast, then the voltage transients can be cause damage.

Oscillations usually can be handled in a few different ways, one is to have a ferrite bead (FB) on each individual FET gate (Which I already know you have), the FBs would ideally dampen the oscillation by having a high impedance at the oscillation frequency, that is why it is important to choose a FB that will target it.

Another way is to have a fixed resistor instead of the FBs, which will dampen the oscillations, but in turn would also slow down your switching speed somewhat, as the resistance will always be there at any frequency. You could try testing while having a fixed resistor here.

Another thing that would help, is to have good layout practices to reduce parasitic components as much as possible. Matched gate traces, small turn-off loops, design traces for low inductance. All of these would help prevent for oscillations. Even the FET selection would be good, FETs with smaller differences in the gate-source threshold voltages would also be less susceptible to the effects of oscillations.

I actually touch on this topic a couple years ago in our yearly live BMS Seminar, here is the PDF of this presentation:http://www.ti.com/lit/SLYP856

I linked to some app notes that aid in the design of MOSFET layouts and circuits. I describe turn-off circuits here as well and the resources here also have explanation on those.

Something else I want to comment on, did you also try running this same test by the DSG pin R29 resistor? For example a 1-kOhm resistor?

Best Regards,

Luis Hernandez Salomon

Thanks lot for sharing the document. I will go through it and understand

One more thing observed during testing, within 50 us Pack+ (source of discharge MOSFET) and and Gate is reaching to zero and current is zero. MOSFET is safe also.

But somehow, Pack+ is again rising to BAT+ and gate is following again. However current is zero in this case so MOSFET must be off. But I am not able to understand Why PACK + is again rising after coming to Zero. Does Cf and Rf connected at pack+ cause issue? I have selected the lowest value recommended in datasheet. What can cause PACK+ to rise again as there is no other capacitor than cf.

Hello Monica,

There is something I just noticed. The Q3 drawing seems to be incorrect, the body-diode is backwards, correct? If the body-diode of the FET is correct there, it would mean the diode bypasses the DSG FET. 

Now for your new question, is there a load attached during the time PACK+ rises? 

If it rises temporarily after it goes low, this is likely due to the transient I described earlier. Now, if it is a more constant value, it may just be leakage currents causing it to rise in voltage.

Best Regards,

Luis Hernandez Salomon

1. That is precharge MOSFET.  It is symbol mistake but in actual it is reverse. Using RD3P130SP in circuit, Diode is propely connected.

It is rsisin to BAT+ value steadily like RC filter output for 100 us and stable for 50us and then again steadily decreasing.

Does Rf, Cf can affect. I have used same recommended values. I tried to change Rf from 100 to 50 but no change. Can I remove Cf? 

Hello Monica,

You should not remove the Cf capacitor. I do not believe either Rf or Cf would cause this problem. You can see waveform examples of how Rf/Cf can affect the turn-off of the DSG FET in the bq76200 Beyond the Simple Application Schematic application note.

It may be a voltage transient due to board/load parasitics after the FET turn-off. I would imagine that slowing down the turn-off speed would cause that PACK+ transient voltage to decrease.

Best Regards,

Luis Hernandez Salomon

Increase turn off time means by increasing Rdsg resistor? As I mentioned earlier, I tried to change Rdsg from 0 ohm to 1K but there was chnage in oscillations. I can't comment on PCB routing as I can't chnage and verify. 

Hello Monica,

Yes correct. I would suggest to increase it further and see how the transient looks.

You could try changing it to 2-kOhms instead. 

Best Regards,

Luis Hernandez Salomon

Diode?Okay.

One more thing, In EVM board user guise, D2 ( SMCJ75A, 75V tvs diode is DNP) and D3 ( part number - ES3D-E3/57T) is connected which is 200V. However Pack+ maximum voltage is 70V. 

Should I connect D2 across it to restrict tranisient? What is the purpose of 200V ?

Hello Monica,

D2 is for positive transient protections, if you want transient protections, I'd recommend to add it. The PACK+ abs max voltage is actually 100-V.

Now, the purpose of D2 is a flyback diode, so it can protect against some negative transients. Now, it is not entirely for transient protections, but it can also serve for reverse-charger protections. It is the simplest of reverse-charger protection that could be added. I would not recommend to use this diode for it however. 

The following application note goes over different reverse charger protection circuits:

• bq76200 Reverse Voltage Considerations

My recommendation would be to use the circuit in Section 2 Low Voltage Reverse Voltage Protection. If you want to add a reverse charger protection circuit.

Best Regards,

Luis Hernandez Salomon