LP87644Q1EVM: Question regarding use of LP87644Q1EVM

Hello Lee,

Thanks for reaching out!

I will look into this in more detail by tomorrow but meanwhile you can try to use updated GUI (link below) because I realized you are using older version of GUI. There has been updates to the GUI. 

https://dev.ti.com/gallery/view/PMICInternal/Scalable-PMICs-GUI/ver/4.0.0/  

BR,

Ishtiaque

Hi, Ishtiaque

I tried clicking on the updated GUI link you provided, but I don't see any data.

Even if you search in the Gallery, you can only find up to 3.0.0 as shown below.

Please check again.

Hi Grady Lee,

Sorry that was internal link. Use below one and check. 

https://dev.ti.com/gallery/view/PMIC/Scalable_PMICs_GUI/ver/4.0.0/ 

BR,

Ishtiaque

Hi, Ishtiaque

The updated GUI version (4.0.0) has been delivered to the customer.

I have not yet received an answer to my initial question. Can you check?

Additionally, the customer has made additional inquiries to you as follows.
(e2e.ti.com/.../lp87644q1evm-restore-the-nvm-with-eeprom-unlock-fail-state /5151251#5151251)
Regarding locking, is there any way to change the 0xA3 register setting without replacing the device?
Please check this question as well. You can also respond to the E2E link inquired by existing customers.

Please check. Thank you.

Hi Grady,

The answer to your previous question is that SPMI protocol for our device is custom. It has to be programmed according to given use case. For example It doesn't work if you try to connect two EVMs configured with same NVM settings because they are intended to be used for certain use case.

In order to enable SPMI in the NVM,  Customer has to configure another PMIC as secondary to establish communication. So the NVM has to be configured for multi-PMIC system and when multi-PMIC NVM has been defined, communication between the devices happens automatically over SPMI based on PFSM triggers and states. There is not way to output manually anything over SPMI interface. 

BR,

Ishtiaque  

Hi,Ishtiaque

So, among the questions above (2. Test procedures and Question: HVS_SPMI_PMIC_EVB_test(Question Detail).pptx), is the test method in the document incorrect?
In order to configure and test other PMICs, are there any additional documents that can be referred to other than those mentioned in the question above?

Hello, this is the customer for this question.
Then, which part of the NVMs of each EVB should be updated to verify the Multi-PMIC synchronization behavior using the PMIC EVB 1 & 2 (LP87644Q1EVM 2 set)?
Can you provide me with an example NVM configuration that I can refer to?
Other features are not very relevant, just check the Multi-PMIC synchronization function.

Thank you for your response.
The process you told me was carried out through the GUI.
However, the NVM program for the secondary PMIC has not been created since then.
The NVM validation of the secondary PMIC fails as shown in the attached figure during the NVM configuration, and the program cannot be created.
For the secondary PMIC NVM, the WD_MASK bit cannot be set, but the validation seems to fail because it checks whether the WD_MASK bit is set or not.
(For the primary PMIC, the NVM validation is successful.)

In this regard, our inquiries are as follows.
- Is there anything else I missed or need to check additionally?
- Do I need GUI update for NVM update? (I'm currently using GUI 4.0.0)
- Can I just proceed with the Primary PMIC NVM configuration for 2 boards without the Secondary PMIC NVM configuration?
- Can you provide an NVM program with Multi-PMIC synchronization for LP87644Q1EVM?
  If it is difficult to disclose on the web, please contact the contact information below.
   yjwon@hyvision.co.kr

Hi Won,

YongJu Won said:

- Is there anything else I missed or need to check additionally?

Not sure how it is being done but WD_MASK warning shown is do not care. Have you programmed both PMICs? Can you share the json file. 

YongJu Won said:

- Do I need GUI update for NVM update? (I'm currently using GUI 4.0.0)

You can also try with previous GUI 3.0.0 version if the device is old one but not necessarily this could be the problem if the procedure of programming the devices in not taken care as intended. 

YongJu Won said:

- Can I just proceed with the Primary PMIC NVM configuration for 2 boards without the Secondary PMIC NVM configuration?

No, both PMICs need to be programmed. 

YongJu Won said:

- Can you provide an NVM program with Multi-PMIC synchronization for LP87644Q1EVM?

Currently we do not have such NVM but can be created and that would take some time for us to provide. So if you are okay with timeline of at least within 2 weeks then we can work on this. 

BR,

Ishtiaque

• Is there anything else I missed or need to check additionally?
  • Not sure how it is being done but WD_MASK warning shown is do not care. Have you programmed both PMICs? Can you share the json file. 
  • => I'm not sure if it's because of WD_MASK, but all other configurations have the recommended settings.
    There is no other warning in NVM validation other than WD_MASK.
    I am attaching the json file. (I zipped it once for the upload.)

sample_template_NVM_config_test_master_slave_240509_00.zip

• Do I need GUI update for NVM update? (I'm currently using GUI 4.0.0)
  • You can also try with previous GUI 3.0.0 version if the device is old one but not necessarily this could be the problem if the procedure of programming the devices in not taken care as intended. 
  • => I'm going to start with GUI version 4.0.0

• Can I just proceed with the Primary PMIC NVM configuration for 2 boards without the Secondary PMIC NVM configuration?
  • No, both PMICs need to be programmed.
  • => I got it.

• Can you provide an NVM program with Multi-PMIC synchronization for LP87644Q1EVM?
  • Currently we do not have such NVM but can be created and that would take some time for us to provide. So if you are okay with timeline of at least within 2 weeks then we can work on this.
  • => If so, I would appreciate it if you could provide it later.

Hi Won,

For secondary PMICB I2C1 and I2C2 addresses have to different than for PMICA

Also triggers for state machine must be per PMICA for PMICB.

Would mask following for PMICB since PMICA controls power-up/down through SPMI. 

Would match startup_dest to be same in PMICB as in PMICA. 

Match to PMICA on PMICB

Br, Jari

Thank you for your response.
The NVM validation was carried out by referring to the answer.
The I2C communication of Master PMIC EVB is not working after the update, I will try to debug it further.
In addition, I would like to understand the setting-related content more clearly, and I would like to set up a development start point.
Could you please attach an example json file where Multi-PMIC synchronization works?

Hi Won,

You can try and debug and regarding the example json file. I will work on this and will provide you by end of this week. 

BR,

Ishtiaque