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UCD3138A: Duty Cycle Calculation from EADC output?

Part Number: UCD3138A

I am trying to understand the math in a simple configuration.

For simplicity, I am using a single filter driving DPWM 0 with the EADC DAC as the comparator value, in a voltage control loop.

The input to the EAP is scaled to 1.6V at the full scale output voltage range.

If I want to regulate the DPWM duty cycle to 25% of the Full scale output Voltage range.

Assume the filter is just 100%  pass though( PID is using just P at 100%).

I have a simple question regarding the calculation of the DPWM duty cycle.

Looking at the diagrams, it seems that the duty cycle is proportional to the difference between the input voltage and the DAC voltage.

So, if the EAP voltage is equal to the DAC voltage then the EADC (error)  output is zero.

This would create a duty cycle of zero not 25%....

What am I missing?

schematically....

Vin--->EAP--> COMP -

Vdac----------> COMP+

So Veadc = Vdac - Vin 

if Vin = Vdac then Veadc = 0.

  • Here is the basic block diagram.

    Basically I having trouble understanding how I get a 25% duty cycle when the output voltage feed back is equivalent to the Set point from the DAC.

    It seems the output would be zero at that point. 

  • Hello BatMan,

    You are right that the output would be almost zero at that point. This is limited by the size of the EADC since it is only 6 bits (max of 63). Thus, you cannot have Kp = 1 since the DERR is too small. Kp must be in the hundreds, if not thousands to multiply the DERR to a large enough value. In the UCD training lab code, Kp = 800. If you just want proportional control, a Kp = 10,000 can be a good start. You can then tune it using the Fusion Studio GUI. 

    Regards,

    Jonathan Wong

  • Yes I understand Kp range.

    I see my issue now. I was over simplifying and thinking that the output voltage was directly proportional to the Duty cycle! 

    I can certainly experiment with it.  Thank you.