Hello, to whom it may concern,
I am currently designing PD3.0 source system using TPS65987D with three PDOs 5V,9V,15V each 3A capability. And recently I had taken PD certification test for our product.
Unfortunately there were failed in TD4.1.2 unpowered CC voltage with error message;
"Error Message: TD.4.1.2.V.3, TD.4.1.2.V.5, TD.4.1.2.V.7 The PUT's CC voltage is not in vOPEN range."
Result: 934mV < min 1.65V spec, @ Default Rp/1.5V@Rp, 1.65V < min 2.75V spec @ 3A Rp.
The test had conducted in other testlab (using LeCroy M310e), but we don't have M310e so that I tried to reproduce the symptom by using very simple method, just plug/unplug the sink device(USB-C-PD-DUO-EVM, SNK mode)
The test results I had done are different from the results obtaind by testlab, the vOPEN is around 3.3V stable.
The question is how I should do a similar test condition to be like M310e ?
Or is there any trick to change VIF/*.pjt file to improve vOPEN voltage (or somehow..) ??
I am ready to send VIF/*.pjt file to you but It may have confidential info so please let me know if you have any comments.
Regartds,
Tsuchida