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UCC14140-Q1: Output is not detected after few minutes first VDD and EN is applied.

Part Number: UCC14140-Q1

Dear TI experts,

My customer now tests UCC14140-Q1 and UCC23133-Q1 in their own PCB.

I reviewed these schematic with another expert ;

UCC14140-Q1 : https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1272684/ucc14140-q1-looking-for-the-reference-for-single-output-system-configuration

UCC23133-Q1 : https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1273989/ucc23313-q1-please-review-the-schematic

the problem is, this PCB worked well right after they made their 1st sample withe the result of these reviews above.

But they made 2nd sample, some layouts are changed, abnormal output is appeared.

1. Applied main voltage 12V and IO voltage 5V -> applied EN pin high of both UCC14140-Q1 and UCC23133-Q1 -> VDD output is fall down to 0V after about 5~30 seconds.

2. In this situation, they have to apply EN pin high 2~5 times, and VDD output is normally detected.

3. no load is connected on the output. (FET side)

I attach the PCB layout of 1st sample (working well) and 2nd sample (not working well). Could you review these 2 layouts? (schematic are the same between these 2 layouts.)

8446.Layout.zip

Best regards,

Chase

  • Hi Chase, I reviewed your layout and please find my feedback below,

    -For Single output configuration, Rlim should not be connected to VEE, but to VDD or leave it floating as last option.

    -Input side/Primary caps:

    • Place 100nF C5 cap next to the (VINP-GNDP) pins 6-8 or 7-9.
    • Place 10uF C3 and C4 caps next to 100nF caps.
    • 0ohm resistor R17 does not need to be next to the, you can place it at the left side of the input caps.

    -Output side/Secondary caps:

    • Place 100nF C37 caps next to (VDD-VEE) pins 29-27 or 28-36. Turn it 90 degrees, so it is in vertical position.
    • Place 10uF C36 next to C37.

    -Feedback resistors R3 and R4. They look good.

    Thank you.