LMR51450: LMR51450FNDRRR

Hi Erez,

Could be layout related. Could you post your layout?

Thanks,

Andrew

Hi,

Please find attached scheme and layout.

The signal:

Before the transient, 50-90uSec after transient start and 50-90uSec after transient end is steady.

Best regards,

Erez

Hi Erez,

Could you have the feed forward (C3) capacitor populated with 10pF? That may help with a transient response.

Thanks,

Andrew

Hi Andrew,

The measurement is with 10pF at Cff.

I have investigated it a little farther and I want to share with you and get your opinion.

1. I change the probe measurement (Reducing the ground loop), see attached picture.

2. It seems that the response ("oscillation surge") right after the transient is due to output capacitors ESR and ESL, see attached picture.

3. I have calculated the required Cff base on the following equation and got 74pF, see attached pictures of the equation and Vout with Cff=100pF.

Best regards,

Erez

Hi Erez,

Thanks for your insight. That transient response seems reasonable. Are you satisfied with the transient response? We could try increasing FSW, but we'd have to play around with L and Cout.

Thanks,

Andrew

Hi Andrew,

The DCDC supplying digital circuit, I don't expect that 50mV voltage drop will effect the circuit reliability.

Any way I'm very interesting of getting the most from the DCDC.

I will appreciate you  insight, what is the idle response? what should be changed in order to get there?

Best regards,

Erez

Hi Erez,

I believe the best way to reduce your output ripple would be to reduce the ESR on the capacitors. You have a large amount of capacitance, but I suspect that the large size of the caps may be impeding the transient response. I would recommend using a smaller case size capacitors.

You could try replacing the 100uF you have with 6V rated 47uF's in the smallest size available and see if that improves it.

Thanks,
Andrew

Hi Andrew,

1. I have ordered the 47uF for experiment.

2. The capacitor values I used are from TI WEB-BENCH.

3. I simulated using PSPICE the effect of capacitor ESL and ESR to transient, The simulation result showed that over shoot due to The capacitor ESL, ESR last ~300nSec.

    The overshoot in the loop response that I measured is~10uSec, what lead me to think it's due to DCDC loop response.

4. I have also ordered  the EVAL board, I will update on the transient result.

Best regards,

Erez

LMR51450 loop stability.pptx

Hi Andrew,

Please find attached comparison between EVL board (3.3V with 2X47uF output capacitors) to My circuit (3.3V with 2X00uF output capacitors)

Best regards,

Erez

Hi Erez,

I don't see anything too crazy with what you got in your experiment. What you are getting is already better than what we show in the DS.

Let me know what you get when you replace your COUT with the 47uF's.

Thanks,

Andrew

Hi Andrew,

First picture with  transient response of 2.5V Transient resistor 2.2ohm output capacitors: 2X100uF/63V/X5R + 1X47uF/16V/X5R

Output voltage drop:50mV

Second picture transient response of 2.5V Transient resistor 2.2ohm output capacitors: 3X47uF/16V/X5R

Output voltage drop:60mV

Hi Erez,

Those are quite the spiks on VOUT. Are the measurements you showed with the tip and barrel connection?

Is there anything Noisy on VIN that's causing your circuit to behave that way? Do you get the same results if you connect a DC power supply to that section rather than powering it the way your circuits powering it?

Perhaps you could also try increasing the switching frequency to 1MHz, and see if that helps.

Thanks,

Andrew

Hi Andrew,

1. I used the tip and barrel connection, I investigate it and found out that the probe ground should be connected to additional short ground wire (not the one that carry the transient current), please see picture below:

2. Please see my previous message using 47uF instead of 100uF: voltage drop rise from 50mv (100uF) to 60mV(47uF)

Best regards,

Erez

Hi Erez,

Do you have any way of controlling the slew rate on the load pulser,

Also, the wires you have to the load pulser may create stray inductance. Have you tried soldering these connections? (blue arrows)

Do you have a scope shot of the VOUT pin when it's not connected to the load pulser?

Thanks,

Andrew

Hi Andrew,

1. I can't control the pulser rise time.

2. Please see Vout without transient load (Oscilloscope in A coupling .)

3. Please see measurement with short connection to pulser

Best regards,

Erez

Hi Erexz,

I haven't heard from you for a while. I'll close the thread, if you still need help feel free to keep replying.

Thanks,

Andrew

Hi Andrew,

Apologizing on the late response.

1.In order to isolate the dcdc response, I disconnect it from the circuit load and connect it only to he pulser including constant resistive load.

(The current is 1A/100mv blue line, Yellow: output response, green: pulse)

The following is it's response...

I think the combination of the pulser and the circuit load (ICs...) cause the strange behavior. 

Best regards,

Erez

I Andrew,

Thanks allot for you patient and support.

To summarize our long discussions:

1. When testing dc/dc with transient load, it's output should be disconnected from the circuit. The dc/dc output should be connected to resistive load (simulating a constant current) and transient load. I used 30% of the total current or each current.

2. The output measurement should be done with the smallest ground loop as possible. (tip and barrel connection)

(The probe ground current should be short wire that not carry the transient current)

3. The load connection should be done with the lowest impedance possible (short, thick twisted wires) 

Andrew, I will appreciate if you could add more insights.

Thanks,

Erez

Hi Erez,

Here are some other thoughts I had about this thread:

I use a tool like this to position probes. It helps if you need to adjust input voltage or output current.

https://www.sparkfun.com/products/11784

I also recommend twisting a skinny wire around the probe to cancel the inductance, I'm not sure if you are doing that in this photo. It should look something like the second photo.

From a circuit design perspective, I would definitely recommend dedicating space for a bode plot resistor with a test point to get the frequency response of your system to see if something fishy is going on with the loop response cross-over frequency and phase margin.

Thanks,

Andrew