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TPSM63603: Parameters for Synchronizing to an External Clock

Chris Read
Genius 3345 points
Part Number: TPSM63603

I have some questions that don't seem to be answered in the datasheet:

  1. Are there any requirements for the frequency set by the RRT value versus the frequency of the external clock coming in on the EN/SYNC pin?
  2. Is the TPSM63603 capable of synchronizing to an external clock through the EN/SYNC pin that has spread spectrum characteristics?
  3. If it can support external spread spectrum, is there a range of variability in the incoming clock that the TPSM63603 can synchronize to, and what is it?

Thanks very much,

Chris

  • 0
    TI__Guru 50120 points

    Hello Chris,

    1. There is no requirement on the Rrt value. However I would suggest having the RRT value the same as the clock value so that it can start up at the expected switching frequency, since device starts up in RT mode checking the value of RT to set the switching frequency. If the application then requires a different frequency, then the external clock source can change it. 

    2/3. Once synchronized to an external clock, SPSP will be turned off and disabled.

    Regards,

    Jimmy

  • 0 in reply to Jimmy Hua
    Genius 3345 points

    Thanks for your answers, Jimmy.

    My understanding is that the TPSM63603 has an internal spread-spectrum mode that gets turned off if synchronizing to an external clock.  I believe that's what your 2/3 response is indicating.

    My question regarding spread spectrum relates to the external clock itself.

    How stable does the external clock have to be?  If the external clock frequency varies by ±20% will the TPSM63603 track and sync to those variations.  If those changes in the external clock's frequency are due to that external clock being adjusted by a spread spectrum mechanism, will the TPSM63603 still be able to track/sync to it?

    What range of variability in the external clock can the TPSM63603 track?

    Regards,

    Chris

  • +1 in reply to Chris Read
    TI__Guru 50120 points

    Hello Chris,

    The intention of the external clock is to provide a fixed frequency for synchronization.

    The circuit attempts to lock to the rising edge of the valid synchronization signal and the internal clock frequency should complete a smooth transition to the frequency of the external clock. Phase locking begins once the clock frequency matches the sync signal which is several pulses after the 2048 cycles. 

    I do not think the device is fast enough to detect and track dithering effects on the external sync signal and have that implemented and phase locked on the internal clock frequency. 

    Regards,

    Jimmy 

  • 0 in reply to Jimmy Hua
    Genius 3345 points

    Thanks very much for your prompt response!