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TPS40054: Unstable loop in the 5V

Andres Gomez
Intellectual 430 points
Part Number: TPS40054
Other Parts Discussed in Thread: UCC39002, , UCC29002

Hi.

We are using two TPS40054 chips to get 5.1V and 3.3V outputs, a UCC39002 for load sharing control, and a hot-swap controller for reverse current protection. Our design was working fine, but we had to replace the High- and Low-side FETs in the Buck converter from FDB13AN06A to IRF1018ES. We also replaced the UCC39002 surface-mount with a UCC29002 through-hole. The ratio between Qgs/Qgd is better in the Infineon MOSFETs than the Onsemi ones; however, we are encountering issues with the new MOSFETs. When we connect the load-sharing controller to the circuit, hot swap controller enters in fault mode. However, when we replace the new MOSFETs with the old ones, the problem seems to be resolved.

Additionally, the issue only occurs under no-load or light-load conditions; when we connect a certain load to the output, the power supply starts working again.

Do you have any information on how the MOSFETs and the load-sharing controller might be related in this context?


Infineon

OnSemi

  • 0
    Intellectual 430 points

    It seems like the compensation loop is affected with the new mosfet. This is Vcomp from TPS40054 (Yellow plot). You can see that the Vcomp is 1.5V but then jumps to 2.8V and after several tries, it stabilizes to 1.5V

  • 0 in reply to Andres Gomez
    Intellectual 430 points

    We could solve the problem by decreasing the capacitor in the snubber circuit of the High-side mosfet. Now, it requires less time to stabilize the voltage. My question is, how does the total charge and the parasitic capacitance of a mosfet affects the switching? Do we need to recalculate Cboost and CBP10? Because, it is shown how to calculate those components in the Datasheet, but it was selected selected the default values

  • 0 in reply to Andres Gomez
    TI__Mastermind 23685 points

    Hi Andres,

    I'm looking into this and I'll provide an answer on Monday.

    Thanks,

    Andrew

  • 0 in reply to Andrew Kutzler
    TI__Mastermind 23685 points

    Can you provide a schematic of your design for me to review?

    Thanks,

    Andrew

  • 0 in reply to Andrew Kutzler
    Intellectual 430 points

    Unfortunately, we cannot provide the entire schematic in public. The image shows what the DS basically states to do for the TPS40054. The problem still remains in the new MOSFETs for the 5V converter. We reduced the snubber capacitor just to get the power supply working. However, we haven't found the reason why the new MOSFETs are failing and the old MOSFETs are still good.

    This is the gate signal for the high-side FET. The power supply is operating in DCM since there are no loads in the output, but you may notice that there are times when the driver cannot maintain the gate voltage and it drops.

  • 0 in reply to Andres Gomez
    TI__Mastermind 23685 points

    Hi Andres,

    The only thing I can think of that the new MOSFETS are introducing a pole somewhere you didn't intend. Have you messed around with any of the other parameters like your Inductor out output capacitance? It may be beneficial to add some low ESR 10uF capacitors if you haven't already and increase the L value.

    Thanks,
    Andrew

  • 0 in reply to Andrew Kutzler
    Intellectual 430 points

    I noticed that QGD/QGS > 1 with the new mosfets, and the old mosfets has QGD/QGS≦１.Do you think this may affect the performance of the SR converter? Because the problem only appears in no-load or light load conditions.

  • 0 in reply to Andres Gomez
    TI__Mastermind 23685 points

    Hi Andres

    Yeah the QGD/QGS > 1 ratio can be a problem, that pops up in transient behavior.

    I've seen these a a possible solution where 1 and 3 are probably the easiest to implement/test:

    1) Slowing the rate of rise of the common (switch) node of the totem pole.  This allow more time to remove some of the Gate-Drain charge without charging the gate-source capacitance.  This can be achieved by added a series gate resistor to the other MOSFET, or in cases of a floating bootstrap drive, adding a resistor in series with the bootstrap capacitor.

    2)  Improving the ability of the gate-drive to remove charge from the gate during the switching node transition.  This can be pretty hard, but typically involved careful attention to layout, eliminating unnecessary path length, loop area or extra resistance in the driver to gate and FET source to driver return paths.

    3) Adding additional gate-source charge through external capacitors.  Adding a 1nF external capacitor from gate to source of the FET typically adds about 4nC of gate-source charge with about 2nC before the FET reaches its threshold voltage, providing some additional protection, however this requires extremely careful attention to layout since any inductance in the capacitor's loop will impede it's ability to absorb Gate-Drain charge.

    Thanks,

    Andrew

  • 0 in reply to Andrew Kutzler
    Intellectual 430 points
    Andrew Kutzler said:
    3) Adding additional gate-source charge through external capacitors.  Adding a 1nF external capacitor from gate to source of the FET typically adds about 4nC of gate-source charge with about 2nC before the FET reaches its threshold voltage, providing some additional protection, however this requires extremely careful attention to layout since any inductance in the capacitor's loop will impede it's ability to absorb Gate-Drain charge

    do I need to apply that change in both FET?

  • 0 in reply to Andres Gomez
    TI__Mastermind 23685 points

    Yeah, I believe you gotta do it to both FETS.

    Thanks,

    Andrew

  • 0 in reply to Andrew Kutzler
    Intellectual 430 points

    Hi Andrew.

    Could you please advice me where to connect the network analyzer in this circuit. If we want to plot the frequency response of the buck controller and then the frequency system of the whole system (buck+load shared controller). 
     
    www.ti.com/.../slua311.pdf

  • 0 in reply to Andres Gomez
    TI__Mastermind 23685 points

    Hi Andres,

    Connect the Network analyzer here to see the frequency response of the buck controller.

    For the UC39002D, I'll let an expert from their team let you know where the best place to connect a network analyzer.

  • 0 in reply to Andrew Kutzler
    TI__Mastermind 40090 points

    Hello Andres, 

    To plot the closed-loop frequency response of a buck converter, typically the voltage feedback network is opened and a resistor is added to provide a place for signal-injection.  In the case of the example shown above, R12 has already been designed in for this purpose for the converter loop. 

    Similar to the perturbing the voltage-loop at the feedback network of the buck converter, a perturbation signal must be injected into the current-sense network of the load-share controller to plot the frequency response of the load-share system.  Since your actual system schematic is not available, I'll use the same example from SLUA311.pdf to indicate where and how to break the current-sense loop.

    Note these important caveats:
    a) The converter + load-share system to be measured, in this case, is a single set of blocks with the buck converter connected to the load-share block connected to the load.  It does not include the other set(s) of converter(s) and its(their) respective load-share controller(s).    
    The LS pin should be opened from the overall system LS bus and the output of the other converter(s) should be disconnected from the load. 
    The "full load" under test, in this case, is 1/N of full system load when all N modules are sharing.  

    b) The CS- input resistor (R16 in the example mark-up, above) must be split into a low-value injection resistor in series with another resistor whose value is adjusted so that the total of the two is equal to the original R16 value.  I used 50R in the example above, because R16 is high enough to allow the 50R injector (to match to a 50R coaxial cable impedance) and not be a significant part of the total input resistance.  Designs with low-value input resistors will need correspondingly lower injection resistances.  

    c) The network analyzer input signal is intended to be a small signal perturbation of a steady-state condition, so (like the voltage loop) it should be about ~1% of the usual full-scale signal.  The problem here is that often the full scale current-sense voltage may be only a few tens of mV, 1% of that is in the 100's of uV.  
    I suggest to practice establishing the perturbation signal level (say 100uV, for example) across the intended injection resistor completely separated from the system until it is proven that you are able to reliably generate the voltage level that you want to inject.  Then connect the injector into the proper position (shown above). 

    d) The reason why the other sets of the overall load-share system are disconnected is because the perturbation affects only one current-sense path, but if the other sets are connected, they will react to the effects of the perturbation on the overall system output and their responses will compound the perturbation on the converter/load-share set being measured.  It will not be clear what the actual gain/phase response of the target set is.

    The above discusses where to inject the signal; the load-share-loop response is measured at the output voltage AFTER the current-sense resistor. 

    Regards,
    Ulrich
      

  • 0 in reply to Andrew Kutzler
    Intellectual 430 points

    Hi Andrew,

    If we have an NDA with TI, how should I send the schematic privately? We are still dealing with the issue of instability with no loads.

  • 0 in reply to Andres Gomez
    TI__Mastermind 40090 points

    Hello Andres, 

    I will send an email to you, to which you can reply with your schematic.  I will then forward the file to Andrew as well, so he can analyze the TPS parts of it. 

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    TI__Mastermind 23685 points

    I got the email and I'll look over it with the team.

    Thanks,

    Andrew