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TPS7A96: PG Trip Point

Part Number: TPS7A96

LDO team,

Can you help with explaining a little more about the PG trip point for the TPS7A96?  If the Rfb Top and Bottom is set to 187K and 12.4K respectively in order to give a 3.3V output, the resulting Vfb_pg = 0.205V.  This is actually lower than the max value for FB_PG pin trip point (rising), which is 0.21V (on page 7 of the datasheet).  If 0.21V is really the trip point for PG, then this would be concerning since the voltage may never reach this trip point.

However, my understanding is that the PG pin will go high at 95% of 0.21V, based on the Note on page 29.  So PG will be high when Vfb_pg reaches 0.1995V. 

Is that correct?

Thanks,
Darren

  • Hi Darren,

    The internal voltage being compared is typically 0.2V with a 5% tolerance.  In a nominal use case, 3.3V is divided down to compare against 0.2V to set the threshold at which the fast charge changes over to the steady state values.  With 12.4k and 187k resistors the math becomes:

    0.2V * (187k + 12.4k) / 12.4k = 3.216V.  This is 97.5% of 3.3V so the fast charge changes over to steady state at 97.5% of the desired Vout.

    Calculating for the worst case values of the threshold voltage:

    0.19V * (187k + 12.4k) / 12.4k = 3.055V, which is 92.6% of 3.3V

    0.21V * (187k + 12.4k) / 12.4k = 3.38V which is higher than 3.3V and you would see the LDO overshoot on turn on by 80mV. 

    If you need to design by worst case analysis then you'll need to consider the upper range of this threshold (0.21V) in your math (you'll also need to consider resistor tolerances which are neglected in these calculations).  This basically means your lower worst case value will probably be closer to 90% of Vout during the changeover, instead of 92.6% calculated above.

    Thanks,

    Stephen