LP876242-Q1: How to close the PMIC watchdog by software?

Hi,

currinwang said:

How can I use software to configure and disable the PMIC watchdog?

Are you talking about application software or GUI which is used to evaluate PMIC using EVM? If the software is related to AM2732 SoC then please ask this question to SoC team on how to use that.   

currinwang said:

And how do I use the PMIC watchdog if it's not closed?

What do you mean by if it is not closed? Do you want to know how enable it or do you want to know if it is already enabled then how can you disable it ?

You can also refer to Watchdog enabling and configuration in 7.3.8.2 (Watchdog Start-Up and Configuration) section of datasheet . 

What is the OPN of the device? Can you specify that.

BR,

Ishtiaque 

Thanks for reply, I just want to know how to use SPI to control the shutdown of PMIC watchdog

Another question I would like to ask is how to configure a register with an offset of 40x?

Hi,

There are two situations in which watchdog (WD) can be disabled. 

1. When the device powers up, WD can be disabled by setting WD_EN bit to 0 (see below) during the Long-Window time-interval defined by • WD_LONGWIN[7:0]. 

WD_EN bit can be written to 0 as ;  0x409 (WD_THR_CFG register) =  0xBF , currently this register value should read 0xFF. 

2. Another situation is when WD is running properly and gets feed by the MCU, now if you want to stop the WD then you have to set WD_RETURN_LONGWIN bit which makes WD return to long window and if you want to hold there then right after that you have to set WD_PWRHOLD to 1. 

This is explained in 7.3.8.4 Watchdog Disable Function section of datasheet as well. 

currinwang said:

Another question I would like to ask is how to configure a register with an offset of 40x?

Can you specify which register you want to configure? because then you need to see whether you are able to configure or not. 

BR,

Ishtiaque 

Thanks a lot. The registers that I may configure include: 0x409, 0x406, 0x405.

May I ask why 0x409 corresponds to 0xBF?

Thanks.

Hi 

currinwang said:

The registers that I may configure include: 0x409, 0x406, 0x405.

yes as I explained above depending on how you want to disable the WD whether during start up or after when the WD is up and running. Please note what I mean by WD up and running is that WD is properly fed by the MCU. 

currinwang said:

May I ask why 0x409 corresponds to 0xBF?

Because WD_EN bit is 0 so with that it becomes 0xBF in hexadecimal for WD_THR_CFG register. By default it would be 0xFF with WD_EN set to 1.  This is when you want to disable WD during start up by WD_EN bit. 

BR,

Ishtiaque

Another issue is that when I access the register of PMIC through SPI, the offset address of the register is single byte.

How should I configure an address greater than 1 byte such as 0x409?

Hi,

The 4 in "0x409" represents page no is SPI communication protocol as shown below from DS. 

You did not mentioned whether you are using GUI of EVM or SoC software. I am not familiar with application software if it is the case. This depends on how the page number has been taken care in software interface. 

BR,

Ishtiaque

Thanks a lot. And I'm using SoC software - mmWave2ChipCascade project based on mcu_plus_sdk_am273x_08_05_00_24. So how should I configure page numbers?