TPS1641: TPS1641 lacking UVLO

Perhaps it would be possible by EN pin of TPS1641...it seems there is hysteresis between enable rising and falling thresholds however it is not explicit. I would like to know what is hysteresis level. Based on values of the table below I can say there can be no hysteresis and it depends on certain part. 

However PSice showed desired behaviour.

Hi Tomas,

Hysterisis will always be there. You can use resistor divider method as shown in EVM user guide on product page.

Regards

Kunal Goel

Hello Kunal,

Is there any chance TI determine at least typical hysteresis? 

Hi Tomas,

I am not sure if that data is readily available. You can always design for worst case values as per datasheet. 

Regards

Kunal Goel

I'm not sure if we can understand each other. This is exactly what I try to solve.
Venr - EN rising threshold minimum is not defined...
Venf - EN falling threshold maximum is not defined...

Hypothetically, the datasheet admits a case where for example Venr=0.6V and Venf=0.59V, as you can see from this example the hysteresis is rapidly reduced.
When it comes to hysteresis and worst case as you said, there is zero hysteresis!!! This quite clashes that you said "Hysterisis will always be there".
Do you already understand me?

Hi Tomas,

Let me check and get back on this.

Regards

Kunal Goel

OK thanks, meanwhile I measured hysteresis on my sample of TPS16411 - it seems to be 50mV.

Thanks Tomas.

Thank you so much!
I have additional question. I would like to have tDLY around 2ms, is it possible?
12nF capacitor is minimum acceptable?

Which slew rate do you mean? I thought 12nF CDLY capacitor for tDLY.

Sorry .  I meant equation that gives TDLY based on CDLY.

I tried to set CDLY to 2n2 and applied test load pulse. It seems that blanking is not working at all, just thermal shutdown after significantly longer time turns off FET.
Do I do anything wrong or this is not possible for TPS1641? If I'm not wrong inside the silicon there is just current source when it comes to PDLY pin, why should it be impossible to connect smaller capacitor then 12nF... It seems like a big limit for my application.

Hi Tomas,

Please try to capture a waveform like this. What do you mean by not working? How much duration you see? It should be around 1ms.

Regards

Kunal Goel

Hello Kunal, I measured this and prepared document where is hopefully everything you need for evaluation.TPS16411_testing.pdf

We need to zoom into this region to know exact timer duration. 

Regards

Kunal Goel

Hi Tomas,

It is around 50us delay. Looks like at lower cap at PDLY below 10nF the timer duration is not as per datasheet equation and might be similar to PDLY open. 

Regards

Kunal Goel