CSD19536KTT for this mosfet can someone provide thermal resistance for minimum copper layout and 1 sq inch pad layout so that we can calculate power dissipation for them.
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CSD19536KTT for this mosfet can someone provide thermal resistance for minimum copper layout and 1 sq inch pad layout so that we can calculate power dissipation for them.
Hello karan,
Thanks for your interest in TI FETs. TI only specs RθJA and RθJC in the FET datasheet. As shown in the blog at the link below, RθJA is measured with the FET with the device suspended in free air (no forced convection). RθJC is measured to the drain tab. I have checked some other vendors datasheets for D2PAK FETs and they spec RθJA = 40°C/W with the device surface mounted on a 1in² Cu pad. It should be about the same with the TI FET. Please let me know if you have any questions.
https://www.ti.com/lit/ta/ssztb80/ssztb80.pdf
Best Regards,
John Wallace
TI FET Applications