• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 63 subscribers
  • Views 270 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM5122: Overload Protection

Tomas Kucera
Prodigy 200 points
Part Number: LM5122

Hello,

We have DC/DC convertor with LM5122 and we have problem with Overload Protection (or shortcurrent) in dual phase interleaved operation.  

We have these parameters:

Input voltage: 24V (20-28V).  

Output voltage: 59V

Output power: 460W

Complete schematic is below. 

Output voltage, output power, heating looks like good. But when we testing overload, device is very often demaged (LM5122 or power transistors BSC123N08NS3). When we testing only single source (second source LM5122 is turn off), overload or over current protection operate very good. Problem is in MASTER/SLAVE mode. 

Best regards, Tomas.  

  • +1
    TI__Mastermind 29750 points

    Hi Tomas,

    Thanks for using the e2e forum and describing the issue in detail.

    Just to clarify the behavior, can you give feedback on the following questions:
    - The the damage occurs, is it always the same FETs that are affected, or does it happen on each phase?
    - How is the overload performed? Is there an actual short on the output side, or is the load increase above the max load settings?

    I cannot directly point out any flaws within the schematic regarding OCP.
    If OCP is only triggered at one phase, both phases should react in parallel, as RES and SS pin are connected with each other.
    This means it should not happen that just one phase shuts down and the other phase is taking twice the load.

    Your design shows that both phases have their own SS and RES cap.
    I would recommend to use just one SS cap and one RES cap for both phases. This might reduce the risk of one phase reacting with a delay due to parasitics.

    I will also check within the team if we ever encountered similar failures, where only phase takes damage.

    Thanks and best regards,
    Niklas

  • 0 in reply to Niklas Schwarz
    Prodigy 200 points

    Hello Niklas,

    Thank you for your quick response. 

    No, the same transistors are not always destroyed, sometimes on master side, sometimes on slave side. Sometimes the upside transistors, the sometimes downside transistors. 

    No, now we testing only overcurrent, we decreasing the resistor on output stage (increasing output current). We have programmable electronic DC load (Axiomet AX-EL600W). Or this DC/DC convertor is for your power audio amplifier TAS5634DDV, and we testing for full load (4 Ohm and 350W audio output power). And we increasing input modulation over the maximum range. 

    I will tried to unfitted the SS and RES capacitors (C353 and C362). Thank you for your good advice. If you have any other idea, I will be very grateful. 

    Best Regards, Tomas. 

  • +1 in reply to Tomas Kucera
    TI__Mastermind 29750 points

    Hi Tomas,

    Thanks for the feedback.
    Here are some additional comment I have after reviewing the design together with the team:

    - Next to the caps on SS and RES from the previous reply, please also disconnect RT resistor on secondary side (R354).
    This signal comes from sync_out of primary side
    -  They are using a 5mOhm sense resistor. Worst case OCP trigger is at 87.5V per datasheet. This would be an inductor current of 17.5A, which is above the inductor current ratings. They can consider increasing the sense resistance of both phases, to avoid saturation current risks.

    And here some additional design comments:
    - The connection at R300 to supply voltage is loose in the schematic picture. is there a connection?
    - There are resistors at the SW pin (R315 & R365). These do not have a function and can be set to 0 Ohm resistors
    - The output elko caps are rated for 63V. If there is an overshoot on Vout, there is very little margin to the abs max

    To check if there is any abnormal switching behavior within the phases in overload operation, it might be helpful to measure the 4 gate signals at the same time. If the application is still failing after the recommended modifications, this would be the next step we can look at.

    Best regards,
    Niklas

  • 0 in reply to Niklas Schwarz
    Prodigy 200 points

    Hello Niklas,

    Thank you very much for your quick response and your advices. This is resolve our problem.It was very important unfitted R353 (SS), R354 (RT) and C362 (RES) on Slave side. Change the R365 and R315 to 0R value, was little influence, but we will change too. 

    Thank you very much again. 

    Best regards,

    Tomas.