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UC2843A: buck convert instablity at higher duty cycle

Arrshith rg
Prodigy 50 points
Part Number: UC2843A

Hi,

I have designed a  synschronous buck converter with uc2843A . I have derived slope compensation ramp from pwm output through RCD circuit to generate a adjustable ramp duty cycle. ramp is add to CS pin. The issue which I am facing is that at higher duty cycles like more that 85% ,there is unstablity. in PWM. So I just wanted to know if there is any maximum duty cycle limitation with peak current mode control.  how can I achive stablity at higher dudty cycles?

  • 0
    TI__Mastermind 32975 points

    The theoretical max duty cycle is D=Vout/Vin but when we consider rise/fall times, turn-on/off delay and dead time required to avoid cross conduction under all operation corners, 85% is good. The more slope compensation you add, the more you are making current mode control appear as voltage mode control and if you add too much artificial RAMP your converter will require a Type 3 compensator instead of what would typically be a Type 2. Are you sure the "instability" is not the result of noise on ISENSE, FB or COMP, or dV/dt induced turn-on of the low-side sync MOSFET or mismatched delays between HS and LS gate drive or sync MOSFET body-diode reverse recovery noise? 

    Regards,

    Steve

  • 0 in reply to Steven Mappus1
    Prodigy 50 points

    The instability is seen just after 85% duty cycle. there is no issue with noise at Isense pin. If dead time is added to the low side PWM the high side remains same.