TPSM33615: Switching Frequency and Low Load Ripple

Part Number: TPSM33615

Tool/software:

Hello everyone,

We are currently using the TPSM33615RDNR as a step-down converter from 24 to 14 volts at low load. In our standard circuit, a jumper is provided on the RT pin to ensure that the controller runs at 2.2 MHz, as recommended.
However, this results in approximately 300 mV of ripple with frequencies between 6 and 10 kHz at the input and output, as well as a noticeable coil whine.

We therefore connected the RT pin to VCC for testing, which resolved the issue. The controller now runs at 1 MHz, with a maximum ripple of 30 mV.

However, we have encountered an unexpected outcome. When we allowed RT to float, the controller exhibited the same good behavior. According to the data sheet, however, this is not recommended practice.

Please explain why this is the case and why the behavior does not match the data sheet.
I have never encountered a similar issue with TI.

Best regards,
Fabian

  • Thank you for the post and apologies for not being able to address it today.

    Please wait for the next business day and the an appropriate engineer will help service this post.

  • Hello Fabian,

    It is generally not recommended to have the RT floating.

    The functional safety information document mentions that this is a Class C if the RT pin is left floating.

    In this case, "frequency is undefined" 

    When we allowed RT to float, the controller exhibited the same good behavior

    Did you also check to see what switching frequency the device was in when RT is floated and device was regulating Vout?

    If you want to operate the device in 2.2MHz, the RT pin should be just hard shorted to GND.

    For 1MHz, RT pin should be connected to VCC. 

    Regards,

    Jimmy

  • Thank you for your answer.

    Yes, I know that floating is not recommended, however, both VCC and GND on the RT pin resulted in coil whine and indefinable switching frequency. Only floating RT provides about 1 MHz switching frequency and acceptable ripple and thus an usable operating condition.

    There are therefore recommended conditions in which the DCDC converter does not work and non-recommended conditions in which the DCDC converter does work.

  • Hello,

    Please share the schematic and PCB layout of the application and an apps engineer can help assist the review.

    It sounds like there may be something in the schematic (inductor or design instability) that may be causing this issue.

    Regards,

    Jimmy

  • Sorry for the late answer.
    Here are the requested schematics and layout (4 layer).


  • Hello,

    The schematic looks ok.

    I have the following comments on the layout:

    • The input capacitors are far from the Vin pin of the device. They must be placed close to the IC in order to reduce the trace inductance in that loop
      • The output capacitors should also be placed close to the IC following this recommendation
    • The FB trace is routed right next to the SW node. This is not recommended because the SW node can capacitively couple noise into the feedback trace. FB must be routed away from the SW node. You should move the FB divider closer to the FB pin of the IC, then route a trace from Vout. 

    Please refer to Section 8.5 of the datasheet for the layout guidelines.

    Best regards,

    Ridge

  • Could this result also in a device running with 1MHz F_SW instead of 2.2Mhz set by the RT resistor? Or is this behaviour load related?

  • Hello,

    The layout issues should be resolved before we can make more comments on why the behavior is happening.

    Best regards,

    Ridge

  • Hi,

    did a rework of my layout and added a 10pF feedforward cap to the schematic.

  • Hi,

    We are observing the 4th of July holiday. Please note that responses will be delayed.

    Thanks,
    Andrew

  • Tests on our old layout with cut feedback traces and changed signal routing have already been promising. So I think that the new layout will certainly bring improvements.

  • Hello,

    The new layout overall looks OK. One comment: The via for the FB trace could be moved over to the right if possible so that it does not impede the main path of the output current.

    Best regards,

    Ridge