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TPS3850: Enabling watchdog during operation causing WDO to wrongly assert low in SPICE simulation

Avi Cahoon
Prodigy 30 points
Part Number: TPS3850

Tool/software:

I have a SPICE simulation using the TPS3850, enabling the watchdog partway through operation.

From my understanding after, SET0 is pulled low, as long as WDI has a falling edge within the maximum watchdog time (and continues within the frequency window afterwards) WDO should not be asserted low, but in simulation it's getting asserted low in response to the first WDI edge trigger.

I want to know what the reason behind WDO being asserted low here is as it doesn't match what I'd expect from the datasheet

Thanks!

  • +1
    TI__Genius 11650 points

    Hi Avi,

    From the looks of your schematic you watchdog is going from disabled (SET0 = 1 & SET1 = 0) to enabled (SET0 = 0 & SET1 = 0). With your CWD capacitor value of 110pF you have a watchdog upper boundary of ~63.51ms and a lower boundary of ~7.94ms. Accounting for the 500us tSET time to allow the device to recognize the change to the SET pins, you provided a falling edge pulse at ~30ms. Under these conditions I agree with you that WDO should not assert and this looks to be a modeling issue with the TPS3850 spice model.

    Thanks,
    Joshua