Tool/software:
I recently tried to enable the 3+2 operation on a self-designed evaluation-board with 5 CSD95492 Buck-Converters, which are connected as advised in the datasheet.
I set up an I2C-Communication Interface with via ESP32 (I do not use the GUI). The device is communicating without problems. All normal operation conditions are programmable per PAGE like VOUT_COMMAND and FREQUENCY_SWITCH.
The device is working with perfect interleaved PWM-Signals for CHANNEL_A, but on CHANNEL_B only PWMB1 is active with a voltage level between 0V and 3,3V. For PWMB2 the PWM-Signal is left on 1,7V (tri-state), which should only be active when the device is working in DCM-Mode or when phase-shedding is active.
I now tried to set the registers of CHANNEL_B manually via I2C to disable DCM as well as Phase-Shedding or all Phases by overwriting the MFR_SPECIFIC-Registers to the corresponding values.
Here is a short list of my changes to the MFR_SPECIFIC_Registers:
MFR_SPECIFIC_06 (CH_B)
from 1000h (default) -> 0000h (disable auto-DCM-operation for channel B)
MFR_SPECIFIC_20 (CH_B)
from 0000h (was set on One-Phase, which is odd, since the second Buck-stage on CH_B is connected) -> 0001h (to force the device to work in 2Phase-Operation) (THE COMMAND WAS ACCEPTED BUT NOT SAVED ON THE REGISTER)
The other MFR_SPECIFIC-Registers were checked to see, if the default-values still match the values in the datasheet. Here is a short list
MFR_SPECIFIC_15 (CH_B)
default on 0000h -> still true when powered up
MFR_SPECIFIC_13 (CH_B)
default 0185h -> bit 12 is set to 0 which should enable the 2phase operation for output B regarding the datasheet page 41 (5.2.3) -> still true when powered up
MFR_SPECIFIC_14 (CH_B)
default 0005h checking if dynamic phase-shedding is active -> still true after power-up; bit 15 = 0b (DCM disabled) bit3 = phase dropping from 2 to 1 Phase disabled (0b)
MFR_SPECIFIC_03 (CH_B)
returned no phase-current imbalance
The Fault-Registers did not show any activated Fault-Bits either .
I also checked the VREF-Voltage going to the Buck-converters and back through the ICSP-Pins. The voltages are correct and the Pins of the devices are connected correctly.
In the Datasheet, there is a short information in the description of the BSCP2-Pin. Here is a snapshot. (Page 5 in the Datasheet)
The description states, that the second Buck-converter for Phase_b has to be connected AND the NVM-Bit has to be set.
I did not find any statement in the datasheet, what NVM-Bit has to be set and on which register.
This could be the problem, since the device seemingly still works in 4+1 operation but with one Phase of CH_A deactivated. But its weird, that the BPWM2 is held in tri-state.
Can someone please explain, which Bit i have to set and where?
Or could this behavior be the symptom of something else?
Best Regards, Maximilian Scholl
