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UC2846: About UC2846 duty cycle

Part Number: UC2846

Tool/software:

Dear Expert

The issue with the UC2846DWTR chip is: a repair machine with a half bridge TOP circuit, burning half bridge MOS. Testing has found that the open loop duty cycle of the upper and lower tubes is asymmetric, with 57% for the upper MOSFET and 43% for the lower MOSFET, and there is no dead zone. May I ask under what circumstances does this happen.

Below is sch ;

3531.pdf

  • Hi,

    It looks you use the peak current to control the duty cycle. If this is true, then it is likely that you are in a fundamental challenge, i.e., a half-bridge converter should not be based on a peak current control. You can check current sense to verify the peak current. I guess your current is not symmetrical and with one time reach peak shorter than the other - this would create the transformer dc flux and cause the transformer saturation then damage the converter.

    To what I know there is no easy fix so half-bridge in peak current mode control has been avoided. But it would need you to confirm this first.