TPS3435-Q1: CWD shutdown and SET0 pin option

Hi Aditya,

For TPS3435AFACADDFRQ1 changing SET0 between high and low will only adjust the scaling factor of the watchdog timeout period. You can use you can use the FPGA to short the CWD pin to ground which will allow for enable/disable operation. The 80ms watchdog timeout period is set by an externally adjustable capacitor on the CWD pin. 

Thanks,
Joshua

Hi Aditya,

You would need to implement something similar to the below image in the schematic. Please note that in order to enable/disable the watchdog operation it will require you to power cycle the device between CWD changing the FPGA value from high(watchdog disabled) to low(watchdog enabled). For this reason of complexity I would recommend using either the B pinout or C pinout which are designed to have simple enable/disable operation via either by the SET pins or a WD-EN pin.

Thanks,
Joshua

Hi Aditya,

This is a fine choice as the TPS3431 is the predecessor device to the TPS3435-Q1. For future reference at the end of the year we are planning to release TPS3435CAEBJDDFR that should suit your watchdog timing needs.

Thanks,
Joshua