LM2621: Root Cause for burn marks above pin 7/8

Hi Konrad,

Could you provide the schematic? I'd like to check how the Zener diode is connected at the boot pin.

It's hard to determine what part of the chip damaged under the burn mark although it's near the SW/boot pin. 

For further check, could you check the following items:

1. What's the impedance or resistance between the SW and GND for the damaged device?
2. Could you re-generate the damage issue with the Vout be monitored? I'd like to check whether the Vout is pulled down below Vin;  
   1. If the Vout is pulled down below Vin, the inductor current will increase without control, the peak current limit take no effect for no matter the low-side FET is on or off, the inductor current increases.

Regards

Lei

Hey,

Here's the schematic:

1.) 1K ohm was measured between SW and GND on a destroyed unit.

2.) Working on this; I have a sample of the electro-mechanical lock on order.  Trying to simulate the lock with a dynamic load has not reproduced the issue.  Even shorting the output of the boost to GND doesn't reproduce the issue.

Hi Konrad,

I'll check and give you the feedback early next week.

Regards

Lei

I have now tested with the electro-mechanical lock and I'm unable to reproduce the issue with the lock.

I have found that if I over-voltage the circuit I can reproduce what appears to be a similar failure.  Nothing is connected to the circuit output at the time of the failure

By apply 22V the LM2621 looks like:

At 24V

Is this the expected failure response for over-voltage condition?

Hi Konrad,

Could you send me the layout? I'd like to check whether the main power path from SW pin --> diode --> Cout(Vout) --> Cout(GND) --> GND pin is too long.

And also, could you help measure the SW voltage on LM2621 that works normally? Please make sure the bandwidth of the voltage probe is high enough, such as > 250MHz.

Regards

Lei

Here's a rendered picture of the PCBA

SW pin captures:

Min. Incoming voltage (7V) and Max outgoing current (~1A):

typical (9V in and ~12V/0.6A out):

Hi Konrad,

Thank you for providing the information.

As my check, although I'm not quite sure the path from the C5 GND to chip PGND pin in your layout, the main path from SW pin --> diode --> Cout(Vout) --> Cout(GND) --> PGND pin is quite long. So the parasitic inductance in this path is relatively big, in tens or even hundreds of nH. This big parasitic inductance will cause high SW spike in each switching cycle in steady state. 

In you provided SW waveforms (typical condition), we can see that the max SW spike is very close to the abs max of 14.5V. I guess the bandwidth of the oscilloscope you used is low, the high and fast spike may not be captured. So the actual conditions can be more worse. This should be the most possible reason that cause the damage. 

You can refer to the layout concept in datasheet for optimization.

Another check point is that when powering/controlling the lock, whether there will be conditions of the Vout shorted to GND even for a very short duration. The current limit and thermal protection won't take effect when the Vout is shorted to GND.

Just let me know if you see any concerns or have updates.

Regards

Lei