LM5069: Drive output abnormality

Part Number: LM5069

Tool/software:

Dears,

The schematic diagram is as follows. The LM5069 at the bottom is only used for redundancy purposes and is not enabled under normal circumstances. It is only used for the LM5069 above;
Current test situation: Under no-load output conditions, after adding a 3.3V level control signal to ULVO for a short period of time, switching to VIN 24V power supply results in no output from the Gate pin. Adding a 700Ω resistive load to the back end results in normal output. When the load is greater than 1KΩ resistors, there is no output. Currently, we do not know the reason for this. After removing the level control signal, the output is normal. Does adding a level control signal to the ULVO pin affect the chip's operation? Is it related to the load? Our design requirement is to turn off the power supply by using a level signal control at the ULVO pin when there is an abnormal load on the back end. We look forward to your answer. Thank you

  • Hi Chen,

    Can you probe the current and TMR pin voltages along with UVLO and GATE. Please share for both the fail and pass test cases.

    BR,

    Rakesh

  • Hi Rakesh,

    The following image 1 shows a normal startup waveform, while image 2 shows a waveform that cannot be started; The pulse section in the picture is the pulse generated by the power supply when it is first powered on, followed by a period of low-level time when the external control signal is pulled down, and the last section is the time after the control signal is released; The difference between the two images is that the load is different. Image 2 has a light load, while Image 1 has a heavier load than Image 2; I'm not sure if the size of the backend load will affect the driver. Looking forward to your reply, thank you~

  • This looks strange. light load would be easy to start.

    I am looping in my teammate Kunal to help you further debug.

  • Hi Rakesh,

    Do you have any suggestions for this issue?Thank you~

  • I am checking on this. Sorry for delay. 

  • Hi Chen,

    1. You confirm that for load up to 700ohm, VOUT is not coming up and load above 700ohm VOUT is coming?

    2. What is load type used?

    3. I see there are two channels. Both channel of board show this behavior?

    Regards

    Kunal Goel

  • 1、Two 2K resistors are connected in parallel to ground at CA2100,  VOUT is not coming up. Three 2K resistors are connected in parallel and VOUT is coming.

    2、The load mainly consists of capacitive load and resistive load, but removing CA2100 or connectting another 220uF capacitor in parallel on CA2100, and there is still no VOUT

    3、Two channels are powered on at the same time, and the situation is the same. There is no output, and a test has been conducted. After short circuiting the 2.3 pin of the MOS transistor with a wire, there is VOUT, but it seems that the chip is not in the normal output state

    4、Also, to explanation, removing the UVLO control signal of LM5069 can also result in normal output

    Looking forward to your reply, thank you~

  • Hi Beryl,

    I will check and get back on this before tomorrow EOD.

    Regards

    Kunal Goel

  • Hi Kunal,

    Do you have any results,looking forward to your reply, thank you~

  • Hi Beryl,

    How is UVLO control signal logic? I do not see in schematic.

    I will recommend checking your design on EVM also. 

    Regards

    Kunal Goel

  • Hi Kunal,

    The ULVO control signal is an additional low-level signal provided by another power domain which is also converted from an external independent 24V power signal,When the other power supply domain is not powered up, the UVLO will follow the 24V power supply to exceed the undervoltage threshold. When the other power supply domain is powered up, the UVLO will be pulled down for a period of time and then released.looking forward to your reply, thank you~

  • Hi Beryl,

    I will recommend you verify your design on EVM. 

    Regards

    Kunal Goel