LM51231-Q1: Problems when leaving bypass operation

Hello Ludwig,

Thanks for reaching out to us via e2e.

The OVP thresholds of the LM5123 are showing some tolerance
While the nominal values for falling and rising are 105% / 108%, the max values can reach 109% / 111%.

Let's assume your device is settled on the high side and your commanded output voltage is 25.4V.
Then you will see 27.7V as the threshold for falling and 28.2V as the threshold for rising.

The LM5123 will not immediately go into OVP status when the rising threshold is once exceeded.
Instead, it needs to see a voltage above the rising threshold for at least 40 μs without any interruption.

For the falling threshold this is different.
If there is a single short event (spike) below the falling threshold, the OVP status will get reset again.

The difference between these thresholds is only about 0.5V.
So, any noise that id picked up by the pin may reset the OVP status (and consequently the bypass mode).
This is why the datasheet recommends that you should place a VOUT capacitor of 0.1 μF close to the VOUT pin to filter such noise.

In case of the LM51231 these thresholds have been changed.
The nominal percentages are 103% and 110%, which results in a hysteresis of 1.7V (compared to 0.5V in case of the LM5123).

This said, I would not automatically propose trying the LM51231 as a replacement, because it comes with other restrictions / requirements regarding the entry into bypass mode.
The LM51231 will only go into bypass mode, if the voltage between CSP and CSN is greater than 6 mV (VCS-FWD).
So, the current needs to be higher than 10% of the peak current to allow for bypass mode.
In case of a light load, when the load current is below 10% at the moment when Vin rises above 110%, the LM51231 will NOT enter bypass mode and the high side FET remains off.

Best regards
Harry

Hello Ludwig,

There must be some kind of noise (very short negative spikes) which is causing this.
The noise will only have an influence when the input voltage is in a range where these distortions will reach the falling threshold of the OVP comparator.
When the input voltage is higher the spikes may be small enough, so that they will no longer have an impact.

Again:
The LM5123 will needs to see 40µs of continuous OVP status.
If there is any single distortion during that time it will re-start again.

That thin yellow spike shows that the controller kept trying to get into bypass mode and at that point in time it did manage for a short period of time, before the next distortion/reset came in.

From my own measurements, I can tell that such negative spikes may be very short (shorter than the sampling rate), so that it is hard to catch them with any oscilloscope.
I had tried to capture them on the LM5123 EVM when looking for an explanation for a different case, where in DE mode the upper FET may get turned off earlier than expected.

Best regards
Harry

Hello Ludwig,

The controller will always go into pulse skip mode when the energy that gets transferred to the output within one cycle is higher than necessary to keep the output voltage stable.
This is usually the case, when the input voltage is close to the targeted output voltage.

It is a misconception that the high side gate driver is always supplied by the charge pump.

The bootstrap capacitor between SW and HB pin is the energy storage for the high side gate driver.
During regular (switching) operation, this capacitor is charged in the following way:
While the low side FET is on, the switch node gets pulled to GND.
At this time, some current will flow from VCC across the built in diode to the HB pin and charge this capacitor.
So the voltage on the bootstrap capacitor will be a little bit lower than VCC.
If there are undershoots, so that the switch node voltage is falling below zero, the voltage on that capacitor can also become higher than VCC.

This is the regular mechanism that works during Boost and pulse skip mode.
If there is quite some high leakage on that capacitor, either internal to the capacitor (self-discharge) or external on the gate output (e.g. a resistor from gate to source), it may get discharged very quickly.
So, during the long gaps in skip mode, you may not see a voltage there and the on-time of the low side FET will be the only moment when that capacitor gets charged (just right before the successive on-time of the high side FET).

The charge pump will only get activated when the controller decides to operate in bypass mode and when in addition pin 14 is pulled high.
The voltage that the charge pump generates is somewhat lower than the VCC voltage (minimum 3.75V) and the charge pump can only deliver a low current.
Therefore, again, any additional leakage may "steal" that energy, so that the FET cannot turn on properly.

To enter bypass mode, it will need to stay in OVP mode for at least 40 µs without any interrupt.
Any short spike due to some noise will re-start this 40µs counter.
And this 40µs timer is basically the only differentiation between Deep Sleep mode (no switching) and bypass operation (high side FET permanently on).

All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults” and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml).

Best regards
Harry